TLFD500 datasheet(4/38 Pages) TI1

4 / 38 page

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AMP1INP– AMP4INP

11,2,66,59

Auxiliary amplifier 1–4 positive input

AMP1INM– AMP4INM

10,3,65,60

Auxiliary amplifier 1–4 negative input

AMP1OUTP– AMP2OUTP

9,4

Auxiliary amplifier 1–2 positive output. Outputs are self-biased to AVDD_TX/2.

AMP3OUTP– AMP4OUTP

64, 61

Auxiliary amplifier 3–4 positive output. Outputs are self-biased to AVDD_RX/2.

AMP1OUTM– AMP2OUTM

12,1

Auxiliary amplifier 1–2 negative output. Outputs are self-biased to AVDD_TX/2.

AMP3OUTM– AMP4OUTM

67,62

Auxiliary amplifier 3–4 negative output. Outputs are self-biased to AVDD_RX/2.

AVDD_REF

Analog supply for reference circuit

AVDD_RX

48,68

RX channel analog supply

AVDD_TX

TX channel analog supply

AVSS_REF

Analog supply return for reference(analog ground)

AVSS_RX

49,69

RX channel analog supply return (analog ground)

AVSS_TX

TX channel analog supply return (analog ground)

COMPDAC1

TX channel decoupling cap input A. Add 1

µF capacitor to AVDD_TX

COMPDAC2

TX channel decoupling cap input B. Add 1

µF capacitor to AVDD_TX

DGPO

Direct general-purpose output. This pin reflects the last value written to the DGPO bit

location in the SDR data stream. It is a general-purpose output that does not require a

secondary transfer to control.

DVDD

31,39

Digital power supply

DVDD_IO

Digital I/O buffer supply

DVDD_RX

RX channel digital supply

DVSS

34,40,41

Digital ground

DVSS_IO

Digital I/O buffer supply return (digital ground)

DVSS_RX

52,54,55,

56,57

RX channel digital supply return (digital ground)

FSX

Serial port frame sync transmit signal

FSR

Serial port frame sync receive signal

GPIO0–GPIO7

23–30

I/O

General-purpose I/O

HPF1INP

RX channel stage 1 amplifier positive input. Input signal needs to have AVDD_RX/2

common mode voltage.

HPF1INM

RX channel stage 1 amplifier negative input. Input signal needs to have AVDD_RX/2

common mode voltage.

HPF2INP

RX channel stage 2 positive input. Input signal need to have AVDD_RX/2 common mode

voltage.

HPF2INM

RX channel stage 2 negative input. Input signal need to have AVDD_RX/2 common mode

voltage.

HPF1OUTP

RX channel stage 1 amplifier positive output. Used to connect external components to obtain

stage 1 HPF.

HPF1OUTM

RX channel stage 1 amplifier negative output. Used to connect external components to

obtain stage 1 HPF.

HPF2OUTP

RX channel stage 2 positive output. Output signal has AVDD_RX/2 common mode voltage.

HPF2OUTM

RX channel stage 2 negative output. Output signal has AVDD_RX/2 common mode voltage.

MCLKIN/PLLCLKIN

Multiplexed pin based on value of PLLSEL. Selects master clock input, or clock input for PLL

mode.

TLFD500 Datasheet(PDF) 4 Page - Texas Instruments

TLFD500 Datasheet(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL