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TLFD500 Datasheet(PDF) 5 Page - Texas Instruments |
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TLFD500 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 38 page ![]() TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION NC 36,53, 58, 63 No connection. Keep floating. PLLSEL 42 I Selects between VCXO mode and DPLL mode. If the pin is tied high PLL mode is selected. Pin should be tied low for VCXO mode. Cannot be left floating. PWRDN 17 I Power-down pin. When PWRDN is pulled low the device goes into power-down mode. The default state of this pin is low. REFM 45 O Negative reference filter node. This terminal is provided for low-pass filtering of the internal band-gap reference. The optimal ceramic capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic), connected to analog ground. The nominal dc voltage at this terminal is 0.5 V. REFP 46 O Positive reference filter node. This terminal is provided for low-pass filtering of the internal band-gap reference. The optimal ceramic capacitor value is 10 µF (tantalum) 0.1 µF (ceramic), connected to analog ground. The nominal dc voltage at this terminal is 2.5 V. RESET 38 I Device reset input pin. Initializes all the device’s internal registers to their default values. The default state of this pin is low. RXBANDGAP 43 O RX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V band-gap reference. The optimal capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic). This node should not be used as a voltage source. RXINP 70 I RX channel stage 3 positive input. The input is self-biased at AVDD_RX/2. RXINM 71 I RX channel stage 3 negative input. The input is self-biased at AVDD_RX/2. SCLK 19 O Serial port shift clock (transmit and receive) SDR 20 I Serial data receive from DSP SDX 18 O Serial data transmit to DSP TXBANDGAP 14 O TX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V band-gap reference. The optimal capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic). This node should not be used as a voltage source. TXOUTP 5 O TX channel positive output TXOUTM 6 O TX channel negative output VCXOCNTL 13 O DAC output to control onboard VCXO VMID_RX 50 I/O Decoupling Vmid for ADC. Add 10 µF (tantalum) and 0.1 µF (ceramic) capacitors to analog ground. VSS 80 I Substrate. Connect to analog ground. detailed description transmit The transmit channel is powered by a high performance DAC. The transmit channel update rate is 276 kHz. The DAC is a 14-bit DAC at 4.416-MHz. This provides 16X oversampling. A band-pass filter limits the output of the transmitter to a frequency range of 30 kHz to 138 kHz. A differential amplifier drives the output into the external line driver. The differential amplifier has programmable attenuation for added flexibility. The transmitter high-pass filter can be bypassed by writing the appropriate bit to the filter bypass control register (BCR). The output spectrum of the DAC complies with the nonoverlapped power spectrum density (PSD) mask specified in the ITU draft recommendation G.992.2 for G.Lite. The TXPAA is a programmable-attenuation amplifier. It provides 0 dB to 24 dB of attenuation in1-dB steps. The TXPAA is controlled via the PAA control register (PCR). For details about register programming see the register programming section. |
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