TLFD500 datasheet(3/38 Pages) TI1

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TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

functional block diagram

MCLKIN

Serial

Interface

and

Control

General

Purpose I/O

Digital

HPF

Digital

LPF

DAC

LPF

Equalizer+

RX LPF

HPF2

HPF1

INTERNAL

REFERENCE

Clock

Generator

VCXO

DAC

External

VCXO

PAA

SCLK

SDX

SDR

FSX

FSR

TXOUTP/

TXOUTM

RXINP/

RXINM

HPF2OUTP/

HPF2OUTM

HPF2INP/

HPF2INM

AMPOUTP/

AMPOUTM

HPF1OUTP/

HPF1OUTM

HPF1INP/

HPF1INM

AMPINP/

AMPINM

TXBANDGAP/

RXBANDGAP

REFM

REFP

VMID_RX

VCXOCNTL

30 kHz to 138 kHz

30 kHz

138 kHz

AUX Amps(4)

GPI00–GPI07

138 kHz

14 Bit

4.416 MSPS

552 kHz

0 to –24 dB

(–1 dB/step)

TX PAA

14 Bit

4.416 MSPS

552 kHz

0 to 9 dB

(0.25 dB/Step)

RX PGA3

0 to 18 dB

(6 dB/step)

RX PGA2

180 kHz

0 to 12 dB

(3 dB/Step)

RX PGA1

180 kHz

35.328 MHz

ADC

Analog

Loop-back

PGA

Digital Loop-back

276

KSPS

1104

KSPS

DPLL

INTERNAL CLOCK

External

Oscillator

35.328 MHz

MCLKIN

See Note

NOTE: Refer to Figure 17 for application details.

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