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TLFD500 Datasheet(PDF) 32 Page - Texas Instruments |
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TLFD500 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 38 page ![]() TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) serial port (see Figures 7 and 8) and DGPO (see Figure 9) PARAMETER MIN TYP MAX UNIT tc1 Period, SCLK 28.3 ns td1 Delay time, FSR high before SCLK ↓ 7 ns td2 Delay time, FSR high after SCLK ↓ 7 ns td3 Delay time, FSX high before SCLK ↓ 7 ns td4 Delay time, FSX high after SCLK ↓ 7 ns td5 Delay time, SDX data valid after SCLK ↑ 7 ns td6 Delay time, GPIO becomes valid after data is sent 7 ns tf Falling time, SCLK change from high to low 4.4 ns th1 Hold time, SDR keep valid after SCLK ↑ 2 ns tr Rising time, SCLK change from low to high 4.6 ns tsu1 Setup time, SDR valid before SCLK ↑ 6 ns tc1 tr tf td1 td2 tsu1 th1 D15 D14 D13 D12 D11 SCLK (Output) FSR (Output) SDR (Input) Figure 10. Data Transfers From DSP to TLFD500PN SCLK (Output) FSX (Output) SDX (Output) td3 td4 td5 Figure 11. Data Transfers From TLFD500PN to DSP |
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