TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

28

POST OFFICE BOX 655303

DPLL detailed description (continued)

To prevent variation in the serial clock width (SCLK) due to jitter, the serial clock is modified to have a fixed high

level of 14 ns and a low level of 7 ns, thus resulting in a period of 21 ns. The average clock frequency is still

35.328 MHz. After the 16 SCLKs are complete, the clock goes quiet (no toggle zone) until the rising edge of

the next ADCLK. The length of the

no-toggle zone varies with the ADCLK. Figure 9 illustrates an example.

SCLK

35.328 MHz

ADCLK

2.208 MHz

DACLK

4.416 MHz

14 ns

7 ns

1/35.328 MHz

Figure 9. Relation of SCLK With ADCLK/DACLK in DPLL Mode

Supply voltage, AVDD to AGND, DVDD to DGND

–0.3 V to 4.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AGND

–0.3 V to AVDD+0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range

–0.3 V to DVDD+0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40

°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

250

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supply

MIN

NOM

MAX

UNIT

Supply voltage

AVDD_RX, AVDD_TX, AVDD_REF

3

3.3

3.6

V

Supply voltage

DVDD, DVDD_IO, DVDD_RX

3

3.3

3.6

V

digital inputs

MIN

NOM

MAX

UNIT

High-level input voltage, VIH

Digital power supply=3 3V

2.4

V

Low-level input voltage, VIL

Digital power supply = 3.3 V

0.6

V

analog input

MIN

NOM

MAX

UNIT

Analog input signal range

AVDD_RX = 3.3 V, The input signal is measured single ended.

AVDD_RX/2

±0.75

V

Analog input signal range

AVDD_RX = 3.3 V, The input signal is measured differentially.

3

Vp-p