TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207B – JUNE 1999 – REVISED MAY 2000

7

POST OFFICE BOX 655303

detailed description (continued)

–100

–150

–200

–250

0

0.5

1

–50

0

f – Frequency – Hz

50

1.5

2

× 105

–4

–6

–8

–10

1

1.2

1.4

–2

0

f – Frequency – Hz

2

1.6

1.8

2

× 105

(a) RX-Stage HPF1 Frequency Response (0 to 200 kHz)

(b) RX-Stage HPF1 Frequency Response (100 kHz to 200 kHz)

kHz

38.6

90.6

142.

6

194.

6

246.

6

298.

6

–27

–24

–21

–18

–15

–12

–

9

–

6

–

3

0

(c) RX-Stage HPF2 Frequency Response (PGA1 = PGA2 = 0 dB)

Figure 1. RX Stage HPF1 and HPF2 Frequency Response

clock control – VCXO mode

The VCXODAC uses a 12-bit, 2s complement number to control a 0-V to 3-V analog output. The two 8-bit

registers, VCR-M and VCR-L, are used to generate the 12-bit control code (2s complement). This implies the

use of 16 bits to obtain a 12-bit number.

VCR-M register occupy the most significant 8 bits in the 12-bit number and the lower 4 bits of the VCR-L register

(VCR-L[3:0] ) are used for the low 4 bits of the 12-bit number. The 12-bit code is updated every time either

register is updated. VCR-L[7:4] must always be zero.