A8521 datasheet(14/35 Pages) ALLEGRO

14 / 35 page

Wide Input Voltage Range, High Efficiency

Fault Tolerant LED Driver

A8521

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Sync

The A8521 can also be synchronized using an external clock

on the FSET/SYNC pin. Figure 8 shows the correspondence of

a sync signal and the FSET/SYNC pin, and figure 9 shows the

result when a sync signal is detected: the LED current does not

show any variation while the frequency changeover occurs. At

power-up if the FSET/SYNC pin is held low, the IC will not

power-up. Only when the FSET/SYNC pin is tri-stated to allow

the pin to rise, to about 1 V, or when a synchronization clock is

detected, will the A8521 try to power-up.

The basic requirement of the sync signal is 150 ns minimum on-

time and 150 ns minimum off time, as indicated by the specifica-

tions for tPWSYNCON and tPWSYNCOFF. Figure 10 shows the timing

for a synchronization clock into the A8521 at 2.2 MHz. Thus any

pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to

synchronize the IC.

The SYNC pulse duty cycle ranges for selected switching fre-

quencies are:

SYNC Pulse Frequency

(MHz)

Duty Cycle Range

(%)

2.2

33 to 66

30 to 70

15 to 85

0.800

12 to 88

0.600

9 to 91

If during operation a sync clock is lost, the IC will revert to the

preset switching frequency that is set by the resistor RFSET. Dur-

ing this period the IC will stop switching for a maximum period

of about 7 μs to allow the sync detection circuitry to switch over

to the externally preset switching frequency.

If the clock is held low for more than 7 μs, the A8521 will shut

down. In this shutdown mode the IC will stop switching, the

input disconnect switch is open, and the LEDs will stop sinking

current. To shutdown the IC into low power mode, the user must

disable the IC using the PWM pin, by keeping the pin low for a

period of 32,750 clock cycles. If the FSET/SYNC pin is released

at any time after 7 μs, the A8521 will proceed to soft start.

Figure 9. Transition of the SW waveform when the SYNC pulse is

detected. The A8521 switching at 2 MHz, applied SYNC pulse at 1 MHz;

shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC (ch3,

2 V/div.), and SW node (ch4, 20 V/div.), time = 5 μs/div.

Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch

node; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC

(ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 μs/div.

SW node

2 MHz operation

1 MHz operation

FSET/SYNC

IOUT

VOUT

150 ns

T = 454 ns

154 ns

PWSYNCON

PWSYNCOFF

Figure 10. SYNC pulse on and off time requirements.

SW node

FSET/SYNC

IOUT

VOUT

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