A8521 datasheet(22/35 Pages) ALLEGRO

22 / 35 page

Wide Input Voltage Range, High Efficiency

Fault Tolerant LED Driver

A8521

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Input overcurrent protection and disconnect switch

The primary function of the input disconnect switch is to protect

the system and the device from catastrophic input currents during

a fault condition. The external circuit implementing the discon-

nect is shown in figure 28. If the input disconnect switch is not

used, the VSENSE pin must be tied to VIN and the GATE pin

must be left open.

When selecting the external PMOS, check for the following

parameters:

• Drain-source breakdown voltage V(BR)DSS > –40 V

• Gate threshold voltage (make sure it is fully conducting at

VGS = –4 V, and cut-off at –1 V)

• RDS(on): Make sure the on-resistance is rated at VGS = –4.5 V or

similar, not at –10 V; derate it for higher temperature

The input disconnect switch has two modes of operation:

• 1X mode

When the input current is between one and two times

the preset current limit value, the disconnect switch enters a con-

stant-current mode for a maximum duration of 10,000 cycles or

5 ms at 2 MHz. During this time, the Fault flag is set immediately

and the disconnect switch goes into a linear mode of operation,

in which the input current will be limited to a value approximate

to the 1X current trip point level (figure 29). If the fault corrects

itself before the expiration of the timer, the Fault flag will be

removed and normal operation will resume.

The user can also during this time decide whether to shut down

the A8521. To immediately shut down the device, pull the FSET/

SYNC pin low for more than 7 μs. After the FSET/SYNC pin has

been low for a period longer than 7 μs, the IC will stop switching,

the input disconnect switch will open, and the LEDx pins will

stop sinking current. The A8521 can be powered-down into low

power mode. To do so, disable the IC by keeping the PWM/EN

pin low for a period of 32,750 clock cycles. To keep the discon-

nect switch stable while the disconnect switch is in 1X mode, use

a 22 nF capacitor for CC and a 20 Ω resistor for RC.

Figure 28. Typical circuit showing the implementation of the input

disconnect feature.

GATE

RADJ

RSC

To L1

VSENSE

VIN

A8521

VIN

Figure 29. Showing typical wave forms for a 3-A, 1X current limit under a

fault condition; shows fSW = 800 kHz, ¯F¯¯A¯U¯¯L¯¯T¯ (ch1, 5 V/div.), IIN (ch2, 2 A/

div.), GATE (ch3, 5 V/div.), and PWM/EN (ch4, 5 V/div.), time = 5 ms/div.

GATE

PWM/EN

IIN

FAULT

(1) Initial fault

detected

(2) Disconnect switch

goes into a linear mode

(4) After 12.5 ms,

disconnect switch

shuts down

(3) IIN limited to 3 A

Figure 30. 2X mode, secondary overcurrent fault condition. IIN is the input

current through the switch. The Fault flag is set at the 1X current limit, and

when the 2X current limit is reached the A8521 disables the gate of the

disconnect switch (GATE); shows ¯F¯¯A¯U¯¯L¯¯T¯ (ch1, 5 V/div.), GATE (ch2,

10 V/div.), IIN (ch3, 2 A/div.), and PWM/EN (ch4, 5 V/div.), time = 5 μs/div.

GATE

PWM/EN

IIN

FAULT

Fault flag set at

1X trip point

A8521 shuts down at

2X trip point

A8521 Datasheet(PDF) 22 Page - Allegro MicroSystems

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