 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
A8521 Datasheet(PDF) 3 Page - Allegro MicroSystems |
|
|
|||||||||||||||||||||||||||||
A8521 Datasheet(HTML) 3 Page - Allegro MicroSystems |
|
|
3 / 35 page  Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8521 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Pin-out Diagram Terminal List Table Number Name Function 1 GATE Output gate driver pin for external P-channel FET control. 2 VSENSE Connect this pin to the negative sense side of the current sense resistor RSC. The threshold voltage is measured as VIN – VSENSE . There is also a fixed current sink to allow for trip threshold adjustment. 3 VIN Input power to the A8521 as well as the positive input used for current sense resistor. 4 ¯F¯¯A¯¯¯U¯¯L¯¯T¯ Indicates a fault condition. Connect a 100 kΩ resistor between this pin and the required logic level voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs. 5 COMP Output of the error amplifier and compensation node. Connect a series RZ-CZ network from this pin to ground for control loop compensation. 6 APWM Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the internal ISET current. 7 PWM/EN PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also used to enable the A8521. 8 FSET/SYNC Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin can also be used to synchronize two or more A8521s in the system. The maximum synchronization frequency is 2.3 MHz. 9 ISET Connect the RISET resistor between this pin and ground to set the 100% LED current. 10 AGND LED signal ground. 11,12,13,14 LEDx Connect the cathodes of the LED strings to these pins. 15 VDD Output of internal LDO; connect a 0.1 μF decoupling capacitor between this pin and ground. 16,17.18 PGND Power ground for internal DMOS device. 19 OVP Overvoltage Condition (OVP) sense; connect the ROVP resistor from VOUT to this pin to adjust the overvoltage protection. 20 SW The drain of the internal DMOS switch of the boost converter. –PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA On 2-layer PCB, 3 in.2 40.0 ºC/W On 4-layer PCB based on JEDEC standard (estimated) 29.0 ºC/W *Additional thermal information available on the Allegro website 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GATE VSENSE VIN FAULT COMP APWM PWM/EN FSET/SYNC ISET AGND SW OVP PGND PGND PGND VDD LED1 LED2 LED3 LED4 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
