AFE4490 datasheet(23/70 Pages) TI

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Timer Compare

16-Bit Register 11

16-Bit Counter

Timer Compare

16-Bit Register 1

Start

Stop

Timer Compare

16-Bit Register 2

Start

Stop

Timer Compare

16-Bit Register 3

Start

Stop

Timer Compare

16-Bit Register 4

Start

Stop

Timer Compare

16-Bit Register 5

Start

Stop

Timer Compare

16-Bit Register 6

Start

Stop

Timer Compare

16-Bit PRF Register

PRF

Pulse

Timer Compare

16-Bit Register 7

Start

Stop

Timer Compare

16-Bit Register 8

Start

Stop

Timer Compare

16-Bit Register 9

Start

Stop

Timer Compare

16-Bit Register 10

Start

Stop

START-A

STOP-A

START-B

STOP-B

START-C

STOP-D

START-D

STOP-D

RED LED

IR LED

Sample RED

Reset

Counter

Reset

SIR

Sample IR

SR_amb,

Sample Ambient

(red phase)

SIR_amb,

Sample Ambient

(IR phase)

CONVR,

Convert RED Sample

CONVIR,

Convert IR Sample

CONVIR_amb,

Convert Ambient Sample

(IR Phase)

CONVR_amb,

Convert Ambient Sample

(RED Phase)

ADC

Conversion

Timer Module

Enable

CLKIN

START

STOP

Set

Reset

Enable

Timer Compare Register

Start Reference Register

Stop Reference Register

Counter

Input

Output

Signal

AFE4490

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SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013

For the 11 signals in Figure 30, the start and stop edge positions are programmable with respect to the PRF

period. Each signal uses a separate timer compare module that compares the counter value with

preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI

interface.

When the counter value equals the start reference value, the output signal is set. When the counter value equals

the stop reference value, the output signal is reset. Figure 33 shows a diagram of the timer compare register.

With a 4-MHz clock, the edge placement resolution is 0.25 µs. The ADC conversion signal requires four pulses in

each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the

ADC conversion signal.

Figure 33. Compare Register

The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four

sets of start and stop registers to control the ADC conversion signal, as shown in Figure 34.

Figure 34. Timer Module

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