AFE4490 datasheet(30/70 Pages) TI

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Clocking

Internal

û ADC

TIA

RXOUTP

Stage 2

Gain

RXOUTN

INP

INN

Device

PD_ALM

ADC_RDY

Use the ADC_Reset

signal on the PD_ALM pin

to clock the external ADC.

Use ADC_RDY to

sync the external

ADC with the AFE.

û ADC

TIA

RXOUTP

Stage 2

Gain

RXOUTN

INP

INN

Device

AFE4490

SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013

www.ti.com

AFE ANALOG OUTPUT MODE (ADC Bypass Mode)

The ADC bypass mode brings out the analog output voltage of the receiver front-end on two pins (RXOUTP,

RXOUTN), around a common-mode voltage of approximately 0.9 V. In this mode, the internal ADC of the

AFE4490 is disabled. Figure 40 shows a block diagram of this mode.

Figure 40. AFE4490 Set to ADC Bypass Mode

In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shown

in Figure 41. This signal can be used to convert each of the four phases (within every pulse repetition period).

Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 42 for

the timing of this mode.

Figure 41. AFE4490 in ADC Bypass Mode with ADC_Reset to PD_ALM Pin

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