 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ORLI10G Datasheet(PDF) 16 Page - Agere Systems |
|
|
|||||||||||||||||||||||||||||
ORLI10G Datasheet(HTML) 16 Page - Agere Systems |
|
|
16 / 72 page  16 Agere Systems Inc. Data Sheet October 2001 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC ORCA ORLI10G Quad 2.5 Gbits/s Receive Path Details (continued) 1333(F) Figure 3. ORLI10G Embedded Core Receive Path Diagram 128 TO 16 MUX OR 64 TO 16 MUX DATA RX_DAT_IN 16 CLOCK RX_CLK_IN 4 FPGA LOGIC DIVIDE BY 8 MODE RX_DAT_OUT[127:96] RX_DAT_OUT[95:64] RX_DAT_OUT[63:32] RX_DAT_OUT[31:0] OR RX_ENB_OUT[3:0] DIVIDE BY 4 MODE RX_DAT_OUT[111:96] RX_DAT_OUT[79:64] RX_DAT_OUT[47:32] RX_DAT_OUT[15:0] RX_CLK8_OUT[0] RX_CLK8_OUT[1] RX_CLK8_OUT[2] RX_CLK8_OUT[3] DIV BY 8 OR DIV BY 4 ORLI10G CORE RX1_PLL (M/N) RX2_PLL (X1) RX1_VCOP (X M/N CLOCK) RX_LOCK RX2_VCOP (X 1 CLOCK) DIV BY 8 OR DIV BY 4 DIV BY 8 OR DIV BY 4 DIV BY 8 OR DIV BY 4 RX_ENB_OUT[3:0] RX1_VCO RX2_VCO |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
