ORLI10G datasheet(45/72 Pages) AGERE

45 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Pin Information (continued)

This table describes the I/O signal ports on the embedded core portion of the device.

Table 17. FPSC Function Pin Description

Symbol

I/O

Description

Control and Global Pins

PLL_BYPASS

3.3 V active-high. Enables the bypass mode for both receive and both transmit

PLLs.

PWRDN

3.3 V active-high. Power down all LVDS links and both receive and both transmit

PLLs.

RESET_RX

3.3 V active-high. Resets the receive PLLs and the demultiplexer block.

RESET_TX

3.3 V active-high. Resets the transmit PLLs and the multiplexer block.

Receive I/O Pins

RX_DAT_IN_N<15:0>

LVDS data input for receive side.

RX_DAT_IN_P<15:0>

LVDS data input for receive side.

RX_CLK_IN_N<3:0>

LVDS clock inputs for receive side.

RX_CLK_IN_P<3:0>

LVDS clock inputs for receive side.

Transmit I/O Pins

TX_DAT_OUT_N<15:0>

LVDS data outputs on transmit side.

TX_DAT_OUT_N<15:0>

LVDS data outputs on transmit side.

TX_CLK_OUT_N<3:0>

LVDS clock outputs on transmit side.

TX_CLK_OUT_N<3:0>

LVDS clock outputs on transmit side.

TX_CLK_IN_N

LVDS transmit reference clock input.

TX_CLK_IN_P

LVDS transmit reference clock input.

LVDS Input Reference Pins

LV_REF10

—

LVDS reference voltage: 1.0 V ± 3%.

LV_REF14

—

LVDS reference voltage: 1.4 V ± 3%.

LV_RESHI

—

LVDS resistor high pin (use 100

Ω to LV_RESLO pin).

LV_RESLO

—

LVDS resistor low pin (use 100

Ω to LV_RESHI pin).

LVCTAP_[6:1]

—

LVDS input centertap (use 0.01 µF to GND).

ORLI10G Datasheet(PDF) 45 Page - Agere Systems

ORLI10G Datasheet(HTML) 45 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL