ORLI10G datasheet(38/72 Pages) AGERE

38 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Timing Characteristics

Receive Input Data Interface

Receive STS-48/STS-192 (2.5G/10G) Data Inputs

Figure 18 illustrates the timing for the receive STS-48/STS-192 data stream. Both the clock and data pins are low-

voltage differential signal (LVDS) input buffers. The expected clock rate is 622 MHz—850 MHz, and the receive

data is clocked on the rising edge of the clock. In 2.5G mode, each of the four channels uses one set of

RX_CLK_INn and 4 RX_DAT_INn data pins. In 10G mode, only RX_CLK_IN0 is used, along with the

RX_DAT_IN[15:0] pins.

5-9085.b (F)

Figure 18. Receive Input Data Timing

Table 14. Receive Data Input Timing

It is recommended that the Rx clock be inverted by crossing the LVDS pin pair, that is, connect the N to the P and

the P to the N. This is because the embedded LI requires the Rx data to be centered on the Rx clock, and typically

the devices that drive the ORLI10G transmit clock and data on the same clock edge. The timing values for the

diagram are given in Table 14.

Symbol

Parameter

–1

–2

–3Unit

Min

Max

Min

Max

Min

Max

Clock Frequency

—

667

—

790

—

850

MHz

Data Setup Time Required

300

—

225

—

210

—

Data Hold Time Required

300

—

225

—

210

—

RX_CLK_IN_[3:0]

RX_DATA_IN_[15:0]

ORLI10G Datasheet(PDF) 38 Page - Agere Systems

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