ORLI10G datasheet(3/72 Pages) AGERE

3 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

Table of Contents (continued)

List of Figures

Page

List of Tables

Page

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Figure 1. ORCA ORLI10G Block Diagram ...............13

Figure 2. 10G (Single-Channel) and 2.5G

(Quad-Channel) Modes .........................................14

Figure 3. ORLI10G Embedded Core Receive

Path Diagram .........................................................16

Figure 4. ORLI10G Embedded Core Transmit Path

Diagram .................................................................18

Figure 5. Demultiplexer Output Data Structure ........20

Figure 6. Demultiplexer Serial-to-Parallel

Conversion—Divide by 8, 10G Mode .....................21

Figure 7. Demultiplexer Serial-to-Parallel

Conversion—Divide by 4, 10G Mode .....................22

Figure 8. Demultiplexer Serial-to-Parallel

Conversion—Divide by 8, 2.5G Mode ....................23

Figure 9. Demultiplexer Serial-to-Parallel

Conversion—Divide by 4, 2.5G Mode ....................24

Figure 10. Multiplexer Input Data Structure ..............26

Figure 11. Multiplexer Parallel-to-Serial

Conversion—Divide by 8, 10G Mode .....................27

Figure 12. Multiplexer Parallel-to-Serial

Conversion—Divide by 4, 10G Mode .....................28

Figure 13. Multiplexer Parallel-to-Serial

Conversion—Divide by 8, 2.5G Mode ....................29

Figure 14. Multiplexer Parallel-to-Serial

Conversion—Divide by 4, 2.5G Mode ....................30

Figure 15. ORLI10G Programmable PLL Block

Diagram .................................................................31

Figure 16. Sample Power Supply Filter Network for

Analog LI Power Supply Pins .................................33

Figure 17. Simplified XGMII Block Diagram .............34

Figure 18. Receive Input Data Timing ......................38

Figure 19. Transmit Output Data Timing ..................39

Figure 20. ac Test Loads ..........................................40

Figure 21. Output Buffer Delays ...............................40

Figure 22. Input Buffer Delays ..................................40

Figure 23. LVDS Driver and Receiver and Associated

Internal Components ..............................................41

Figure 24. LVDS Driver and Receiver ......................41

Figure 25. LVDS Driver ............................................41

Figure 26. Package Parasitics ..................................67

Table 1. ORCA ORLI10G—Available FPGA Logic ... 1

Table 2. Programmable PLL Specifications ............ 32

Table 3. ORLI10G Reset Requirements .................. 32

Table 4. HSTL Input Requirements to FPGA .......... 35

Table 5. Absolute Maximum Ratings ....................... 35

Table 6. Recommended Operating Conditions ....... 35

Table 7. Driver dc Data ............................................ 36

Table 8. Driver ac Data ............................................ 36

Table 9. Driver Power Consumption ........................ 36

Table 10. Receiver ac Data ..................................... 37

Table 11. Receiver Power Consumption ................. 37

Table 12. Receiver dc Data ..................................... 37

Table 13. LVDS Operating Parameters ................... 37

Table 14. Receive Data Input Timing ...................... 38

Table 15. Transmit Data Output Timing .................. 39

Table 16. FPGA Common-Function Pin

Description ............................................................ 42

Table 17. FPSC Function Pin Description ............... 45

Table 18. Embedded Core/FPGA Interface Signal

Description ............................................................ 46

Table 19. ORCA Programmable I/Os Summary ...... 47

Table 20. PBGA Pinout Table ................................. 48

Table 21. ORCA ORLI10G Plastic Package

Thermal Guidelines ............................................... 66

Table 22. Heat Sink Vendors ................................... 66

Table 23. . ORCA ORLI10G Package Parasitics .... 67

Table 24. Device Type Options ............................... 71

Table 25. Temperature Options ............................... 71

Table 26. Package Options ..................................... 71

Table 27. Package Matrix (Speed Grade) ............... 71

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