ORLI10G datasheet(17/72 Pages) AGERE

17 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Transmit Path Details

In the transmit path, the ORLI10G embedded core can

be broken down into three sections: the multiplexer, the

transmit side onboard PLLs, and the high-speed line

interface. Note that both transmit and receive PLLs are

in addition to the four programmable PLLs (PPLLs) in

the FPGA portion of the ORLI10G.

MUX

The multiplexer takes data from the FPGA logic and

multiplexes the data to rates for transfer by the high-

speed line interface. The multiplexer supports two

modes of operation:

Multiplex-by-8

The multiplexer converts the incoming 128 bits of data

at 78 Mbits/s to 106 Mbits/s into 16 bits at 622 Mbits/s

to 850 Mbits/s. The incoming transmit reference clock

is divided by 8.

Multiplex-by-4

10G (or single channel): The multiplexer converts the

incoming 64 bits of data at 156 Mbits/s to 212 Mbits/s

into 16 bits at 622 Mbits to 850 Mbits/s. The transmit

reference clock is divided by 4.

Onboard Transmit PLLs

The function of the onboard PLLs is to align the system

data with the line data which will be at a slightly higher

rate owing to the addition of the overhead bits. There

are two PLLs on the transmit path. The input to the first

PLL, TX1_PLL (see Figure 4), is the divided down

transmit reference clock from the multiplexer. The

TX1_PLL generates a clock with a user-defined fre-

quency ratio of M/N to the divided clock. This clock

would generally be used to compensate for different

data rates due to overhead bits. M and N can be inde-

pendently set from 1 to 8.

The TX2_PLL also takes its input reference from the

divided down reference clock and is used to provide a

balanced divided clock across the FPGA-embedded

core interface.

Both PLLs have delay loops which compensate for

routing delays to the embedded core/FPGA logic inter-

face for minimum clock skew.

In addition, the user can specify an additional skew on

each clock in increments of 1/8 the clock period.

The selection of the MUX width (and corresponding

clock division value), the TX1_PLL M and N values,

and the additional skew for TX1_PLL and TX2_PLL are

specified by the user in a GUI interface provided in the

ORLI10G design kit.

A detailed block diagram of the transmit path in shown

in Figure 4. In 10 Gbit mode, either TX1_VCOP or

TX2_VCOP must be used to clock TX_DAT_IN[127:0]

that is transmitted to the embedded block. These PLLs

can also be bypassed, where the divided transmit ref-

erence clock is sent directly to the FPGA. In 2.5 Gbit

mode, TX_CLK8_IN[3:0] is used to clock data transmit-

ted to the embedded block.

Line Interface

In the transmit path, 16-bit data and associated clocks

are outputs from the line interface. Typical data rates

are expected to range from 622 Mbits/s to 850 Mbits/s

for most applications. The 16-bit LVDS output data bus

is actually composed of four 4-bit data buses with one

clock for each 4-bit data bus. On the transmit side,

these clocks will all be synchronized. The ORLI10G

uses LVDS (low-voltage differential signaling)

drivers/receivers, which are intended to provide point-

to-point connection between the ORLI10G and optical

transceiver (MUX/deMUX) parts. The LVDS drivers are

hot-swap compatible and can connect to other

vendor’s LVDS I/O buffers. The LVDS drivers are

terminated with a 100

Ω resistor to improve

performance.

The transmit line interface on the ORLI10G can con-

nect to devices that are compliant to either the XSBI

standard or the SFI-4 standard. The major difference

for these standards is that for XSBI, the least signifi-

cant bit [0] is transferred first after serialization by the

external MUX device, whereas SFI-4 transmits the

most significant bit first. In some cases, bits [15:0] on

the ORLI10G should be connect to bits [0:15] on the

device to which the ORLI10G device interfaces to. An

example of this is the PCS IP core in the ORLI10G

when the ORLI10G is connected to an XSBI version

2.1 device.

It should be noted that IEEE 802.3ae version 3.1

swaps XSBI so that the most significant bit is trans-

ferred first, thus requiring that bits [0:15] on the

ORLI10G be connected directly to bits [0:15] on the

XSBI device.

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