ORLI10G datasheet(39/72 Pages) AGERE

39 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Timing Characteristics (continued)

Transmit STS-48/STS-192 (2.5G/10G) Data Outputs

Figure 19 illustrates the timing for the transmit STS-48/STS-192 data stream. Both the clock and data pins are

driven with low-voltage differential signal (LVDS) output buffers. The expected clock rate is 622 MHz—850 MHz

and the transmit data is clocked out on the rising edge of the clock. In 2.5G mode, each of the four channels uses

one set of TX_CLK_OUTn with four TX_DAT_OUTn data pins. In 10G mode, only TX_CLK_OUT[0] is used with

the 16 TX_DAT_OUT[15:0] pins. The timing values for the diagram are given in Table 15.

5-9089.c(F)

Figure 19. Transmit Output Data Timing

Table 15. Transmit Data Output Timing

* This requirement is for all sources of the output clocks (e.g., RCLKSI, etc.).

It is recommended that the Tx clock be inverted by crossing the LVDS pin pair, that is, connect the N to the P and

the P to the N. This is because the receiving device that will be driven by the ORLI10G typically requires that data

be centered around the clock, but the ORLI10G drives both the clock and data from the same clock edge.

Symbol

Parameter

–1

–2

–3Unit

Min

Max

Min

Max

Min

Max

Clock Frequency

—

667

—

790

—

850

MHz

—

Duty Cycle

4555

Data Delay from Clock Edge

–300

300

–225

225

–210

210

Data Rise Time: 20%—80%

100

200

100

200

100

200

Data Fall Time: 80%—20%

100

200

100

200

100

200

TX_DAT_OUT[15:0]

TX_CLK_OUT[3:0]

ORLI10G Datasheet(PDF) 39 Page - Agere Systems

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