ORLI10G datasheet(32/72 Pages) AGERE

32 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

ORLI10G Embedded Programmable PLLs Specifications

Table 2. Programmable PLL Specifications

Notes:

Multiplication and division values can both be used on one PLL output (example 3/4x).

For more information, see the Series 4 PLL Application Note.

ORLI10G Reset Requirements

Both the embedded core portion and the FPGA portion are reset at powerup. The embedded core is also reset, as

shown in Table 3, based on other conditions. For version 1 ORLI10G devices, these resets are all asynchronous

and must be held in reset for at least 8 ns. For version 2, the resets can also optionally be set to be asynchronous

on with synchronous release. Table 3 also shows the conditions upon which the I/O are 3-stated.

Table 3. ORLI10G Reset Requirements

Typically, the following reset sequence should be followed for the ORLI10G:

Place the device in reset by driving RESET_TX = 1, RESET_RX = 1, and by placing the FPGA portion into reset.

Release the embedded core from reset by driving RESET_TX = 0 and RESET_RX = 0.

Release the FPGA portion from reset.

Parameters

Min

Nom

Max

Unit

VDD15

1.425

1.5

1.575

VDD33

3.0

3.3

3.6

Operating Temperature

–40

—

125

°C

Input Clock Frequency

—

420

MHz

Input Duty Cycle

—

Input Clock Jitter Requirement

——

TBD

UIp-p

Input Jitter Transfer

——

TBD

UIp-p

Output Clock Frequency

—

420

MHz

Output Duty Cycle

dc Power Consumption

—

Total On Current (dc)

—

Total Off Current (dc)

—

30.0

—

Cycle to Cycle Jitter (p-p)

—

<0.02

TBD

UIp-p

Period Jitter (p-p)

TBD

UIp-p

Duty Cycle Jitter (p-p)

TBD

UIp-p

VCO Output vs. VCOP Output Jitter

——

TBD

Lock Time

—

<50

—

µS

Frequency Multiplication (TX1_PLL and RX1_PLL)

2x, 3x, 4x, 5x, 6x, 7x, 8x

—

Frequency Division (TX1_PLL and RX1_PLL)

1/8x, 1/7x, 1/6x, 1/5x, 1/4x, 1/3x, 1/2x

—

Duty Cycle Adjust of Output Clock(s)

12.5, 25, 37.5, 50, 62.5, 75, 87.5

Delay Adjust of Output Clock

0, 45, 90, 135, 180, 225, 270, 315

degrees

Phase Shift Between VCO and VCOP

0, 45, 90, 135, 180, 225, 270, 315

degrees

Condition

TX MUX Block

TX PLL

RX DeMUX Block

RX PLL

Embedded I/O

Powerup

Reset

3-state

FPGA Configuration

Reset

Active

TS_ALL Pin = 1

——

—

3-state

RESET_TX Pin = 1

Reset

——

Active

RESET_RX Pin = 1

——

Reset

Active

PWRON Pin = 1

—

Powerdown

—

Powerdown

Active

ORLI10G Datasheet(PDF) 32 Page - Agere Systems

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