ORLI10G datasheet(25/72 Pages) AGERE

25 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

ORLI10G Multiplexer (Tx) Detail

The multiplexer module converts the incoming 128 bits

of data from the FPGA logic at 78 MHz/106 MHz or

64 bits of data from the FPGA logic at 156 MHz/212

MHz into 16 bits of data at 622 MHz/850 MHz. It has

been implemented as two stages. The first stage

deinterleaves each incoming byte into a different byte

stream that can be serially output on the output data

pins. The second stage outputs these bytes into 16 bits

or four groups of 4 bits, depending upon the mode of

operation. Functionally, the multiplexer architecture

consists of three blocks: the parallel-to-serial

conversion, the counters, and the deinterleaving.

For 2.5G divide-by-8 mode, the first stage of the line

interface module deinterleaves each incoming byte of

data into a different byte stream on the

78 MHz/106 MHz (TX_CLK8_IN[3:0]) clock. This data

is then registered on the rising edge of the

622 MHz/850 MHz (TX_CLK_IN) clock at the falling

edge of the 78 MHz/106 MHz clock. The enable inputs

(TX_ENB8_IN[3:0]) are used to transfer data from the

low-speed clock to the high-speed clock, as well as

synchronizing the counters of parallel-to-serial

conversion which are running at the high-speed clock.

For 2.5G divide-by-4 mode, the first stage of the line

interface module deinterleaves each incoming byte of

data into a different byte stream on the

156 MHz/212 MHz (TX_CLK8_IN[3:0]) clock. This data

is then registered on the rising edge of the

622 MHz/850 MHz (TX_CLK_IN) clock at the falling

edge of the 156 MHz/212 MHz clock. The enable

inputs (TX_ENB8_IN[3:0]) are used to transfer data

from the low-speed clock to the high-speed clock, as

well as synchronizing the counters of parallel-to-serial

conversion which are running at the high-speed clock.

In 2.5G modes, the enable inputs (TX_ENB8_IN[3:0])

are required to be four (divide by 4) or eight (divide by

8) TX_CLK_IN clock cycles wide. They have to be

synchronous to their corresponding TX_CLK8_IN[3:0]

clock. Each of these four TX_CLK8_IN[3:0] clocks

must also be frequency locked to the TX_CLK_IN

signal.

In 10G modes, the enable inputs (TX_ENB8_IN[3:0])

are also required to be four (divide by 4) or eight (divide

by 8) TX_CLK_IN clock cycles wide. In 10G modes,

the other enable inputs (TX_ENB8_IN[3:1]) are

unused. Unlike 2.5G modes, this enable is

synchronous to a divided version of TX_CLK_IN from

the embedded core. In 10G modes, the

TX_CLK8_IN[3:0] inputs are not used. For version 2

ORLI10G devices, the enable signal can also

optionally be generated automatically in the embedded

core, thus removing the need to supply TX_ENB8_IN0

when that mode is selected. A second new option for

the version 2 ORLI10G devices will synchronize the

TX_ENB8_IN0 enable with the divided version of

TX_CLK_IN in the embedded core to simplify timing.

In both 2.5G and 10G modes, the TX_CLK_OUT[3:0]

clock outputs from the ORLI10G are provided for

transferring each 4 bits of data per clock.

For both 2.5G modes and 10G modes, all data to be

transmitted to the embedded core must be frequency

locked to the TX_CLK_IN signal. Thus, the divided

version of this clock found at the embedded core

interface should always be used to transfer data from

the FPGA logic to the embedded core. In 2.5G modes,

this same clock signal should also be used to generate

the enable signals as discussed previously. These

clock signals are available from the TX PLL outputs

(TX1_VCO, TX1_VCOP, TX2_VCO, TX2_VCOP).

Figure 10 shows the valid data input bits to the

multiplexer in each of the four modes (divide-by-8, 10G

and 2.5G modes, and divide-by-4, 10G and 2.5G

modes). Figure 11—Figure 14 show the multiplexer

input transmit reference clock, data, enable, and clock

waveforms and output clock and data waveforms for all

four modes.

In version 2 of the ORLI10G device, additional

capabilities are added to the Multiplexer block. The first

allows the clock inputs TX_CLK8_IN[3:0] to be

optionally generated in the embedded core in 2.5G

mode, as is done for 10G mode for version 1. The

second option allows all enables TX_ENB8_IN[3:0] to

be generated in the embedded core for both 2.5G and

10 G modes. The third option allows the enable inputs

TX_ENB8_IN[3:0] to continue to be used, but they are

re-synchronized in the embedded core before being

used. All options allow for simplification of the FPGA to

embedded core interface. If none are selected, the

ORLI10G defaults to version 1 compatible operation.

ORLI10G Datasheet(PDF) 25 Page - Agere Systems

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