ORLI10G datasheet(47/72 Pages) AGERE

47 / 72 page

Agere Systems Inc.

Data Sheet

October 2001

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA ORLI10G Quad 2.5 Gbits/s

Pin Information (continued)

Package Pinouts

Table 14 provides the number of user programmable I/Os available for each available package. Table 20 provides

the package pin and pin function for the ORLI10G FPSC and packages. The bond pad name is identified in the

PIO nomenclature used in the ORCA Foundry design editor. The bank column provides information as to which

output voltage level bank the given pin is in. The group column provides information as to the group of pins the

given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-ended

limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then the

VREF pin is available as an I/O pin.

When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the

number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).

When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for

the FPGA. The tables provide no information on unused pads.

Table 19. ORCA Programmable I/Os Summary

It is very important to note the pinout limitations for 10 Gbits/s Ethernet applications. Specifically, the very stringent

timing requirements of the XGMII specification coupled with the I/O availability and locations in the 416-pin PBGA

requires that the XGMII output pins be located on three sides of the device. This may cause issues with routing the

XGMII bus at a board level since the XGMII specification for routing this bus on a board is only 2 in.

In addition, the built-in microprocessor interface (MPI) cannot be fully utilized in the 416-pin PBGA and the 680-pin

PBGA packages because the implementation of the XGMII interface limits the number of available address and

data pins.

As shown in the Pair columns in Table 20, differential pairs and physical locations are numbered within each bank

(e.g., L19C_A0 is the nineteenth pair in an associated bank). A C indicates complementary differential whereas a

T indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or verti-

cal direction. Other physical indicators are as follows:

_A1 indicates one ball between pairs.

_A2 indicates two balls between pairs.

_D0 indicates balls are diagonally adjacent.

_D1 indicates balls are diagonally adjacent separated by one physical ball.

VREF pins, shown in the Pin Description column in Table 20, are associated to the bank and group

(e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank).

Device

416 PBGAM

680 PBGAM

User programmable I/O

192

316

Available programmable differential pair pins

184

272

FPGA configuration pins

FPGA dedicated function pins

Core function pins

VDD15

VDD33_A

VDD33

VDDIO

VSS

VSS_A

LVCTAP for dedicated differential channels

Core LV_REF pins

Total package pins

416

680

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