MSP430F6776IPZ datasheet(34/157 Pages) TI

34 / 157 page

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

www.ti.com

Table 17. Default Port Mapping (continued)

PIN NAME

PxMAPy

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

MNEMONIC

PEU

P3.5/PM_UCA1TXD/

PM_UCA1TXD/

eUSCI_A1 UART TXD (direction controlled by eUSCI – output),

PM_UCA1SIMO

PM_UCA1SIMO/S35

PM_UCA1SIMO

eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)

P3.6/PM_UCA2RXD/

PM_UCA2RXD/

eUSCI_A2 UART RXD (direction controlled by eUSCI – input),

PM_UCA2SOMI/

PM_UCA2SOMI/S34

PM_UCA2SOMI

eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)

P3.7/PM_UCA2TXD/

PM_UCA2TXD/

eUSCI_A2 UART TXD (direction controlled by eUSCI – output),

PM_UCA2SIMO

PM_UCA2SIMO/S33

PM_UCA2SIMO

eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)

P4.0/PM_UCA2CLK

P4.0/PM_UCA2CLK/S32

PM_UCA2CLK

eUSCI_A2 clock input/output (direction controlled by eUSCI)

P4.1/PM_UCA3RXD/

PM_UCA3RXD/

eUSCI_A3 UART RXD (direction controlled by eUSCI – input),

PM_UCA3SOMI/

PM_UCA3SOMI/S31

PM_UCA3SOMI

eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)

P4.2/PM_UCA3TXD/

PM_UCA3TXD/

eUSCI_A3 UART TXD (direction controlled by eUSCI – output),

PM_UCA3SIMO

PM_UCA3SIMO/S30

PM_UCA3SIMO

eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)

P4.3/PM_UCA3CLK

P4.3/PM_UCA3CLK/S29

PM_UCA3CLK

eUSCI_A3 clock input/output (direction controlled by eUSCI)

P4.4/PM_UCB1SOMI/

PM_UCB1SOMI/

eUSCI_B1 SPI slave out master in (direction controlled by eUSCI),

PM_UCB1SCL

PM_UCB1SCL/S28

PM_UCB1SCL

eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)

P4.5/PM_UCB1SIMO/

PM_UCB1SIMO/

eUSCI_B1 SPI slave in master out (direction controlled by eUSCI),

PM_UCB1SDA

PM_UCB1SDA/S27

PM_UCB1SDA

eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)

P4.6/PM_UCB1CLK

P4.6/PM_UCB1CLK/S26

PM_UCB1CLK

eUSCI_B1 clock input/output (direction controlled by eUSCI)

P4.7/PM_TA3.0

P4.7/PM_TA3.0/S25

PM_TA3.0

TA3 CCR0 capture input CCI0A

TA3 CCR0 compare output Out0

System Module (SYS) (Link to User's Guide)

The SYS module handles many of the system functions within the device. These include power on reset and

power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap

loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data

exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

Table 18. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

SYSRSTIV , System Reset

019Eh

No interrupt pending

00h

Brownout (BOR)

02h

Highest

RST/NMI (POR)

04h

DoBOR (BOR)

06h

Wakeup from LPMx.5

08h

Security violation (BOR)

0Ah

SVSL (POR)

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)

10h

SVMH_OVP (POR)

12h

DoPOR (POR)

14h

WDT timeout (PUC)

16h

WDT key violation (PUC)

18h

KEYV flash key violation (PUC)

1Ah

Reserved

1Ch

Peripheral area fetch (PUC)

1Eh

PMM key violation (PUC)

20h

Reserved

22h to 3Eh

Lowest

SYSSNIV , System NMI

019Ch

No interrupt pending

00h

SVMLIFG

02h

Highest

SVMHIFG

04h

DLYLIFG

06h

DLYHIFG

08h

Submit Documentation Feedback

MSP430F6776IPZ Datasheet(PDF) 34 Page - Texas Instruments

MSP430F6776IPZ Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL