MSP430F6776IPZ datasheet(57/157 Pages) TI

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ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

Voltage applied at DVCC to DVSS

–0.3 V to 4.1 V

Voltage applied to any pin (excluding VCORE)(2)

–0.3 V to VCC + 0.3 V

Diode current at any device pin

±2 mA

Storage temperature range, Tstg

(3)

–55°C to 105°C

Maximum junction temperature, TJ

95°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3)

Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

Supply voltage during program execution and flash

VCC

programming. VAVCC = VDVCC = VCC

(1) (2)

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

VSS

Supply voltage VAVSS = VDVSS = VSS

Operating free-air temperature

I version

–40

°C

Operating junction temperature

I version

–40

°C

CVCORE

Recommended capacitor at VCORE

470

CDVCC/

Capacitor ratio of DVCC to VCORE

CVCORE

PMMCOREVx = 0,

1.8 V

≤ VCC ≤ 3.6 V

8.0

(default condition)

PMMCOREVx = 1,

12.0

Processor frequency (maximum MCLK frequency)(3) (4)

2 V

≤ VCC ≤ 3.6 V

fSYSTEM

MHz

(see Figure 2)

PMMCOREVx = 2,

20.0

2.2 V

≤ VCC ≤ 3.6 V

PMMCOREVx = 3,

25.0

2.4 V

≤ VCC ≤ 3.6 V

ILOAD,

Maximum load current that can be drawn from DVCC

DVCCD

for core and IO (ILOAD = ICORE + IIO)

ILOAD,

Maximum load current that can be drawn from

AUX1D

AUXVCC1 for core and IO (ILOAD = ICORE + IIO)

ILOAD,

Maximum load current that can be drawn from

AUX2D

AUXVCC2 for core and IO (ILOAD = ICORE + IIO)

ILOAD,

Maximum load current that can be drawn from AVCC

AVCCA

for analog modules (ILOAD = IModules)

ILOAD,

Maximum load current that can be drawn from

AUX1A

AUXVCC1 for analog modules (ILOAD = IModules)

ILOAD,

Maximum load current that can be drawn from

AUX2A

AUXVCC2 for analog modules (ILOAD = IModules)

PINT

Internal power dissipation

VCC x I(DVCC)

(1)

It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)

can be tolerated during power up and operation.

(2)

The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold

parameters for the exact values and further details.

(3)

The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(4)

Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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