MSP430F6776IPZ datasheet(87/157 Pages) TI

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MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

10-Bit ADC Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

AVCC and DVCC are connected together,

AVCC

Analog supply voltage

AVSS and DVSS are connected together,

1.8

3.6

V(AVSS) = V(DVSS) = 0 V

V(Ax)

Analog input voltage range(1)

All ADC10_A pins

AVCC

Operating supply current into

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,

2.2 V

100

AVCC terminal, REF module

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

µA

3 V

110

and reference buffer off

ADC10SREF = 00

Operating supply current into

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,

AVCC terminal, REF module

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

3 V

124

180

µA

on, reference buffer on

ADC10SREF = 01

IADC10_A

Operating supply current into

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,

AVCC terminal, REF module

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

3 V

105

160

µA

off, reference buffer on

ADC10SREF = 10, VEREF = 2.5 V

Operating supply current into

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,

AVCC terminal, REF module

SHT0 = 0, SHT1 = 0, ADC10DIV = 0,

3 V

110

µA

off, reference buffer off

ADC10SREF = 11, VEREF = 2.5 V

Only one terminal Ax can be selected at one time

Input capacitance

from the pad to the ADC10_A capacitor array

2.2 V

3.5

including wiring and pad.

AVCC > 2.0V, 0 V ≤ VAx ≤ AVCC

Input MUX ON resistance

Ω

1.8V < AVCC < 2.0V, 0 V ≤ VAx ≤ AVCC

(1)

The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external

reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to

decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and

MSP430x6xx Family User's Guide (SLAU208).

10-Bit ADC Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

For specified performance of ADC10_A linearity

fADC10CLK

2.2 V, 3 V

0.45

5.5

MHz

parameters

Internal ADC10_A

fADC10OSC

ADC10DIV = 0, fADC10CLK = fADC10OSC

2.2 V, 3 V

4.4

4.9

5.6

MHz

oscillator(1)

REFON = 0, Internal oscillator,

12 ADC10CLK cycles, 10-bit mode,

2.2 V, 3 V

2.4

3.0

fADC10OSC = 4 MHz to 5 MHz

tCONVERT

Conversion time

µs

External fADC10CLK from ACLK, MCLK or SMCLK,

See

ADC10SSEL

≠ 0

(2)

Turn on settling time of

tADC10ON

See (3)

100

the ADC

RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF

(4)

1.8 V

µs

tSample

Sampling time

RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF

(4)

3 V

µs

(1)

The ADC10OSC is sourced directly from MODOSC inside the UCS.

(2)

12 × ADC10DIV × 1/fADC10CLK

(3)

The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already

settled.

(4)

Approximately eight Tau (

τ) are needed to get an error of less than ±0.5 LSB

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