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MSP430F6776IPZ Datasheet(PDF) 92 Page - Texas Instruments |
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MSP430F6776IPZ Datasheet(HTML) 92 Page - Texas Instruments |
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92 / 157 page ![]() (MSP430F677xIPEU only) P1.0/TA1.1/VeREF-/A0 P1.1/TA2.1/VeREF+/A1 P1.2/ACLK/A2 P1.3/ADC10CLK/A3 1 DVCC DVSS 0 0 0 1 1 0 1 0 1 Bus Keeper D EN 0 0 1 1 0 1 0 1 P1DS.x EN SET Q A0..A3 Interrupt Edge Select From ADC P1REN.x P1DIR.x P1OUT.x From Timer_A, ACLK, ADC10CLK DVSS P1SEL0.x P1SEL1.x P1IN.x To Timer_A P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x MSP430F676x MSP430F674x SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 Through P1.3 Input/Output With Schmitt Trigger (MSP430F677xIPEU Only) 92 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated |
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