MSP430F6776IPZ datasheet(77/157 Pages) TI

77 / 157 page

SDA

SCL

HD,DAT

SU,DAT

HD,STA

HIGH

LOW

BUF

HD,STA

SU,STA

SU,STO

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

eUSCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK, ACLK

feUSCI

eUSCI input clock frequency

External: UCLK

fSYSTEM

MHz

Duty cycle = 50% ± 10%

fSCL

SCL clock frequency

2 V, 3 V

400

kHz

fSCL = 100 kHz

5.1

tHD,STA

Hold time (repeated) START

2 V, 3 V

µs

fSCL > 100 kHz

1.5

fSCL = 100 kHz

5.1

tSU,STA

Setup time for a repeated START

2 V, 3 V

µs

fSCL > 100 kHz

1.4

tHD,DAT

Data hold time

2 V, 3 V

0.4

µs

fSCL = 100 kHz

5.0

tSU,DAT

Data setup time

2 V, 3 V

µs

fSCL > 100 kHz

1.3

fSCL = 100 kHz

5.2

tSU,STO

Setup time for STOP

2 V, 3 V

µs

fSCL > 100 kHz

1.7

UCGLITx = 0

220

UCGLITx = 1

120

Pulse duration of spikes suppressed by input

tSP

2 V, 3 V

filter

UCGLITx = 2

UCGLITx = 3

UCCLTOx = 1

tTIMEOUT

Clock low timeout

UCCLTOx = 2

2 V, 3 V

UCCLTOx = 3

Figure 16. I2C Mode Timing

Schmitt-Trigger Inputs – RTC Tamper Detect Pin

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

AUXVCC3

MIN

TYP

MAX

UNIT

1.8 V

0.80

1.40

VIT+

Positive-going input threshold voltage

3 V

1.50

2.10

1.8 V

0.45

1.00

VIT–

Negative-going input threshold voltage

3 V

0.75

1.65

1.8 V

0.3

0.85

Vhys

Input voltage hysteresis (VIT+ – VIT–)

3 V

0.4

1.0

For pullup: VIN = VSS

RPull

Pullup or pulldown resistor

For pulldown: VIN =

Ω

AUXVCC3

Input capacitance

VIN = VSS or AUXVCC3

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