MSP430F6776IPZ datasheet(91/157 Pages) TI

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ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

Flash Memory (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

tCPT

Cumulative program time

See (1)

Program and erase endurance

104

105

cycles

tRetention

Data retention duration

TJ = 25°C

100

years

tWord

Word or byte program time

See (2)

µs

tBlock, 0

Block program time for first byte or word

See (2)

µs

Block program time for each additional byte or word, except for last

tBlock, 1–(N–1)

See (2)

µs

byte or word

tBlock, N

Block program time for last byte or word

See (2)

µs

Erase time for segment erase, mass erase, and bank erase when

tErase

See (2)

available

MCLK frequency in marginal read mode

fMCLK,MGR

MHz

(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

(1)

The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2)

These values are hardwired into the flash controller's state machine.

JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

fSBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse length

2.2 V, 3 V

0.025

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

tSBW, En

2.2 V/3 V

µs

edge)(1)

tSBW,Rst

Spy-Bi-Wire return to normal operation time

100

µs

2.2 V

MHz

fTCK

TCK input frequency for 4-wire JTAG(2)

3 V

MHz

Rinternal

Internal pulldown resistance on TEST

2.2 V, 3 V

Ω

(1)

Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before

applying the first SBWTCK clock edge.

(2)

fTCK may be restricted to meet the timing requirements of the module selected.

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