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MSP430F6776IPZ Datasheet(PDF) 73 Page - Texas Instruments |
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MSP430F6776IPZ Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 157 page  ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x MSP430F676x MSP430F674x www.ti.com SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK or ACLK, fTA Timer_A input clock frequency External: TACLK, 1.8 V, 3 V 25 MHz Duty cycle = 50% ± 10% All capture inputs. tTA,cap Timer_A capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns capture. eUSCI (UART Mode) Recommended Operating Conditions PARAMETER CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK or ACLK, feUSCI eUSCI input clock frequency External: UCLK, fSYSTEM MHz Duty cycle = 50% ± 10% BITCLK clock frequency fBITCLK 5 MHz (equals baud rate in MBaud) eUSCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT UCGLITx = 0 10 15 25 UCGLITx = 1 30 50 85 tt UART receive deglitch time(1) 2 V, 3 V ns UCGLITx = 2 50 80 150 UCGLITx = 3 70 120 200 (1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. eUSCI (SPI Master Mode) Recommended Operating Conditions PARAMETER CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK or ACLK, feUSCI eUSCI input clock frequency fSYSTEM MHz Duty cycle = 50% ± 10% eUSCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 150 tSTE,LEAD STE lead time, STE low to clock ns UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 150 UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 200 STE lag time, Last clock to STE tSTE,LAG ns high UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 200 2 V 50 UCSTEM = 0, UCMODEx = 01 or 10 3V 30 STE access time, STE low to tSTE,ACC ns SIMO data out 2 V 50 UCSTEM = 1, UCMODEx = 01 or 10 3 V 30 2 V 40 UCSTEM = 0, UCMODEx = 01 or 10 3V 25 STE disable time, STE high to tSTE,DIS ns SIMO high impedance 2 V 40 UCSTEM = 1, UCMODEx = 01 or 10 3 V 25 2 V 50 tSU,MI SOMI input data setup time ns 3 V 30 (1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 73 |
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