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MSP430F6776IPZ Datasheet(PDF) 27 Page - Texas Instruments

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Part # MSP430F6776IPZ
Description  POLYPHASE METERING SoCs
PDF  157 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430F6776IPZ Datasheet(HTML) 27 Page - Texas Instruments

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ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x
MSP430F676x
MSP430F674x
www.ti.com
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 9. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
WORD
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
INTERRUPT
ADDRESS
Comparator_B
Comparator_B Interrupt Flags (CBIV) (1)
Maskable
0FFCAh
37
AES
AESRDYIFG
Maskable
0FFC8h
36
0FFC6h
35
Reserved
Reserved(5)
⋮
⋮
0FF80h
0, lowest
(5)
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte formats.
Legend
rw:
Bit can be read and written.
rw-0,1:
Bit can be read and written. It is reset or set by PUC.
rw-(0,1):
Bit can be read and written. It is reset or set by POR.
rw-[0,1]:
Bit can be read and written. It is reset or set by BOR.
–
SFR bit is not present in device.
Table 10. Interrupt Enable 1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
AUXSWNMIE
–
rw-0
7
6
5
4
3
2
1
0
JMBOUTIE
JMBINIE
ACCVIE
NMIIE
VMAIE
–
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a
general-purpose timer.
OFIE
Oscillator fault interrupt enable
VMAIE
Vacant memory access interrupt enable
NMIIE
Nonmaskable interrupt enable
ACCVIE
Flash access violation interrupt enable
JMBINIE
JTAG mailbox input interrupt enable
JMBOUTIE
JTAG mailbox output interrupt enable
AUXSWNMIE
Supply switched non-maskable interrupt enable
Table 11. Interrupt Flag 1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
JMBOUTIFG
JMBINIFG
–
NMIIFG
VMAIFG
–
OFIFG
WDTIFG
rw-[0]
rw-[0]
rw-0
rw-0
rw-0
rw-0
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG
Flag set on oscillator fault
VMAIFG
Set on vacant memory access
NMIIFG
Set via RST/NMI pin
JMBINIFG
Set on JTAG mailbox input message
JMBOUTIFG
Set on JTAG mailbox output register ready for next message
Copyright © 2012–2013, Texas Instruments Incorporated
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