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MSP430F6776IPZ Datasheet(PDF) 88 Page - Texas Instruments |
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MSP430F6776IPZ Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 157 page  ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x MSP430F676x MSP430F674x SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013 www.ti.com 10-Bit ADC Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V -1.0 +1.0 Integral EI 2.2 V, 3 V LSB linearity error 1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC -1.0 +1.0 Differential (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), ED 2.2 V, 3 V -1.0 +1.0 LSB linearity error CVREF+ = 20 pF (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), EO Offset error 2.2 V, 3 V -1.0 +1.0 LSB Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), EG Gain error 2.2 V, 3 V -1.0 +1.0 LSB CVREF+ = 20 pF Total unadjusted (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), ET 2.2 V, 3 V -2.0 +2.0 LSB error CVREF+ = 20 pF 10-Bit ADC External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Positive external reference VeREF+ VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V voltage input Negative external VeREF– VeREF+ > VREF–/VeREF– (3) 0 1.2 V reference voltage input (VeREF+ – Differential external VeREF+ > VREF–/VeREF– (4) 1.4 AVCC V VeREF–) reference voltage input 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, 2.2 V, 3 V -26 +26 µA Conversion rate 200 ksps IVeREF+ Static input current IVeREF– 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, 2.2 V, 3 V -1 +1 µA Conversion rate 20 ksps Capacitance at VREF+ CVREF+ (5)10 µF terminal (1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. (2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. (3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. (4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). 88 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated |
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