LP3972 datasheet(22/59 Pages) TI1

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msb Register Add lsb

msb Chip Address lsb

start

ack

msb

DATA1

lsb

ack

stop

ack from slave

Data (reg_0x24)

msb

DATA2

lsb

msb

DATA3

lsb

Data (reg_0x25)

Data (reg_0x26)

msb Register Add lsb

msb Chip Address lsb

start

ack

msb

DATA

lsb

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

LP3972

SNVS468J – SEPTEMBER 2006 – REVISED AUGUST 2011

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MULTI-BYTE I2C COMMAND SEQUENCE

To correctly function with the Monahan’s Power Management I2C the LP3972’s I2C serial interface shall support

Random register Multi-byte command sequencing: During a multi-byte write the Master sends the Start command

followed by the Device address, which is sent only once, followed by the 8 Bit register address, then 8 bits of

data. The I2C slave must then accept the next random register address followed by 8 bits of data and continue

this process until the master sends a valid stop condition.

A Typical Multi-byte random register transfer is outlined below:

Device Address,

Note: The PMIC is not required to see the I2C device address for each transaction. A, M, X, and Z are Random

numbers.

Figure 24.

INCREMENTAL REGISTER I2C COMMAND SEQUENCE

The LP3972 supports address increment (burst mode). When you have defined register address n data bytes

can be sent and register address is incremented after each data byte has been sent. Address incrimination may

be required for non XScale applications. User can define whether multi-byte (default) to random address or

address incrimination will be used.

Figure 25.

LP3972 CONTROL REGISTER

Read/Write

8h’07

SCR

R/W

System Control Register

8h’10

OVER1

R/W

Output Voltage Enable Register 1

8h’11

OVSR1

Output Voltage Status Register 1

8h’12

OVER2

R/W

Output Voltage Enable Register 2

8h’13

OVSR2

Output Voltage Status Register 2

8h’20

VCC1

R/W

Voltage Change Control Register

8h’23

ADTV1

R/W

Buck1 Target Voltage 1 Register

8h’24

ADTV2

R/W

Buck1 DVM Target Voltage 2

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