LP3972 datasheet(36/59 Pages) TI1

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LP3972

SNVS468J – SEPTEMBER 2006 – REVISED AUGUST 2011

www.ti.com

Bit

Reset Value

Buck3:2 Voltage Ramp Control Register (B3RC) 8h’87 Definitions

Bit

Access

Name

Description

7:4

R/W

B3RR

Data Code

Ramp Rate mV/µS

4h’0

Instant

4h’1

4h’2

4h’3

4h’4

4h’5

4h’6

4h’7

4h’8

4h’9

4h’A

3:0

R/W

B2RR

Data Code

Ramp Rate mV/µS

4h’0

Instant

4h’1

4h’2

4h’3

4h’4

4h’5

4h’6

4h’7

4h’8

4h’9

4h’A

INTERRUPT STATUS REGISTER ISRA

This register specifies the status bits for the interrupts generated by the PMIC. Thermal warning of the IC,

GPIO1, GPIO2, PWR_ON pin, TEST_JIG factory programmable on signal, and the SPARE pin.

Interrupt Status Register ISRA 8h’88

Bit

Designation

Reserved

T125

GPI2

GPI1

WUP3

WUP2

WUPT

WUPS

Reset Value

Interrupt Status Register ISRA 8h’88 Definitions

Bit

Access

Name

Description

—

Reserved

T125

Status bit for thermal warning PMIC T>125C

0 = PMIC Temp. < 125°C

1 = PMIC Temp. > 125°C

GPI2

Status bit for the input read in from GPIO 2 when set as Input

0 = GPI2 Logic Low

1 = GPI2 Logic High

GPI1

Status bit for the input read in from GPIO 1 when set as Input

0 = GPI1 Logic Low

1 = GPI1 Logic High

WUP3

PWR_ON Pin long pulse Wake Up Status

0 = No wake up event

1 = Long pulse wake up event

WUP2

PWR_ON Pin Short pulse Wake Up Status

0 = No wake up event

1 = Short pulse wake up event

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LP3972 Datasheet(PDF) 36 Page - Texas Instruments

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