Electronic Components Datasheet Search
  English  ▼

X  

LP3972 Datasheet(PDF) 44 Page - Texas Instruments

Click here to check the latest version.
Part # LP3972
Description  Power Management Unit for Advanced Application Processors
PDF  59 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LP3972 Datasheet(HTML) 44 Page - Texas Instruments

Back Button LP3972 Datasheet HTML 40Page - Texas Instruments LP3972 Datasheet HTML 41Page - Texas Instruments LP3972 Datasheet HTML 42Page - Texas Instruments LP3972 Datasheet HTML 43Page - Texas Instruments LP3972 Datasheet HTML 44Page - Texas Instruments LP3972 Datasheet HTML 45Page - Texas Instruments LP3972 Datasheet HTML 46Page - Texas Instruments LP3972 Datasheet HTML 47Page - Texas Instruments LP3972 Datasheet HTML 48Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 44 / 59 page
background image
VCC_RTC
nRSTO
nBATT_FLT
SYS_EN
High-Volt_PD
nRESET_OUT
PWR_EN
Low-Volt_PD
t5
13 MHZ_OSC
PXA27x Output
PXA27x Output
PXA27x Output
PXA27x Output
1.
2.
3,4.
5.
6.
7.
8.
9,10.
t2
t4
t1
t3
Main Batt
VIN
BU Batt
VIN
LP3972
SNVS468J – SEPTEMBER 2006 – REVISED AUGUST 2011
www.ti.com
* Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the
two signals is independent of each other and can occur is either order.
Figure 30.
POWER-ON TIMING
Symbol
Description
Min
Typ
Max
Unit
t1
Delay from VCC_RTC assertion to nRSTO de-assertion
50
mS
t2
Delay from nBATT_FLT de-assertion to nRSTI assertion
100
µS
t3
Delay from nRST de-assertion to SYS_EN assertion
10
mS
t4
Delay from SYS_EN assertion to PWR_EN assertion
125
mS
t5
Delay from PWR_EN assertion to nRSTO de-assertion
125
mS
HARDWARE RESET SEQUENCE
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters
hardware reset state. The LP3972 holds the nRST low long enough (50 ms typ.) to allow the processor time to
initiate the reset state.
RESET SEQUENCE
1. nRSTI is asserted.
2. nRSTO is asserted and will de-asserts after a minimum of 50 mS
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (VIN) is
available.
4. After system power (VIN) is turned on, the LP3972 de-asserts nBATT_FLT.
5. The Applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer.
6. The LP3972 enables the high-voltage power supplies.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer.
44
Submit Documentation Feedback
Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Links: LP3972



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com