ML7344J datasheet(10/151 Pages) ETC2

10 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

10/151

●Power supply/GND pins

Pin name

Reset

state

I/O

Active

Level

function

VDD_REG

−

VDDIO

−

Power supply pin for Regulator

(input voltage: 1.8V to 3.3V)

VDDIO

−

VDDIO

−

Power supply for digital I/O

(input voltage: 1.8 to 3.6V)

VDD_PA

−

VDDIO

−

Power supply for PA block

(input voltage: 18 to 3.6V, depending on TX mode)

VDD_RF

−

VDDRF

−

Power supply for RF blocks

(REG-OUT is connected, typ.1.5V)

VDD_CP

−

VDDRF

−

Power supply for charge pump

(REG-OUT is connected, typ.1.5V)

VDD_VCO

−

VDDRF

−

Power supply for VCO

(REG_OUT is connected, typ.1.5V)

GND_VCO

−

GND

−

GND for VCO

●Unused pins treatment

Unused pins treatments are as follows:

Unused pins treatment

Pin name

Pins number

Recommended treatment

N.C.

Open

N.C.

GND or Open

EXT_CLK

GND

A_MON

GND

GPIO0

Open

GPIO1

Open

GPIO2

Open

GPIO3

Open

(Note)

*1 If input pins are high-impedence state and leave open, excess current could be drawn. Care must be taken

that unused input pins and unused I/O pins should not be left open.

*2 After reset, GPIO1 pin is CLK_OUT function. If this function is not used, the clock must to be disabled by

setting 0b000 to GPIO1_IO_CFG[2:0] ([GPIO1_CTRL: B0 0x4F (2-0)]). If this pin is left open while

outputing clock signal, it may affect RX sensitivity.

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