ML7344J datasheet(78/151 Pages) ETC2

78 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

78/151

The following is timing chart for IDLE detemination exclusion under strong signal.

Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)

Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)

Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0111 (IDLE detection 129.5µs)

[During IDLE_WAIT counting, detected extremly strong signal. After the given signal is out of averaging

target, IDLE detection case]

ED7

INVALID

ED8

ED13 ED14

0x001

0x006

0b11

(on-going)

0x000

ED value>CCA_IGNORE_LVL

detection and reset

Due to extreme strong signal detection,

CCA_RSLT is not indicating IDLE.

CCA_RSLT[1:0]=0b11 do not generate interrupt

ED15

ED21 ED22

0x007

ED29

0b00

(IDLE)

Resume counting due to the extreme

strong signal is out of averaging target.

CCA _RSLT maintains until

IDLE/BUSY detected.

ED VALUE>CCA_IGNORE_LVL

ED value <CCA_IGNORE_LVL

Average ED value<CCA_LEVEL

(If average ED value >CCA_LVL, then BUSY detection)

0b10

(on-going)

ED value

(internal signal)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_PROG[9:0]

[CCA_PROG_L/H:B0 0x3E/3D]

ED value<CCA_IGNORE_LVL

●●●

(0-7)

(1-8)

(6-13)

(7-14)

(8-15)

(14-21)

(15-22)

(22-29)

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