ML7344J datasheet(80/151 Pages) ETC2

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FEDL7344C/E/J-04

ML7344C/E/J

80/151

[ED value 1time IDLE detection case]

Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)

Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b000. (1 time average)

Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 1110 (IDLE detection 259µs)

NOTE:

*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL

([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.

ED value

(internal signal)

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

AD conversion

(18.5μs)

ED value average

period (18.5μs)

0b10 (CCA on-going)

ED1

(0)

0b00 (IDLE)

Do not average

CCA execution period (Min.148μs+18.5μs+259μs =425.5μs)

< CCA_LVL

B0 0x37

ED0

ED2

ED13

ED3

ED14

●●●

(1)

(2)

(12)

IDLE_WAIT[9:0]

[IDLE_WAIT_L\H: B0 0x3C/3B]

IDLE detection period (259μs)

INVALID

0x000

0x001 0x002

0x00C

(average ED value < CCA_LVL)

continue for AD conversion period

14 times (259μs), then IDLE is

determined.

●●●

(13)

(14)

●●●

0x00D 0x00E

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