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ML7344J Datasheet(PDF) 23 Page - List of Unclassifed Manufacturers |
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ML7344J Datasheet(HTML) 23 Page - List of Unclassifed Manufacturers |
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23 / 151 page ![]() FEDL7344C/E/J-04 ML7344C/E/J 23/151 ●Reset characteristics Item Symbo Condition Min Typ. Max Unit RESETN delay time (Power on) TRDL1 All power supply pins (After power on) 0.5 - - ms RESETN pulse period When starting from VDDIO=0V TRPW1 200 - - ns RESETN pulse period 2 When starting from VDDIO ≠0V TRPW2 VDDIO > 1.8V should be required. 1.5 - - ms RESETN input delay time (When ML7344 start up from VDDIO ≠0V) TRDL2 VDDIO > 1.8V 1 - - µs RESETN rising time TRRST - - 1 ms NOTE: When ML7344 start up from VDDIO ≠0V, RESETN pulse should be asserted after VDDIO becomes over 1.8V. VDDIO RESET TRDL1 TRPW1 TRPW2 Less than 1.8V TRDL2 VDD level GND level 1.8V TRRST |
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