ML7344J datasheet(74/151 Pages) ETC2

74 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

74/151

The following is timing chart for continuous mode.

Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)

Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)

Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0000 (IDLE detection 0µs)

[BUSY to IDLE transition, terminated with CCA_STOP]

NOTE:

*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL

([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.

(21-28)

(43-50)

ED value

(Internal signal)

AD conversion

(18.5μs)

ED value average period

(148μs)

0b10 (CCA on-going)

ED0

ED7

ED8

ED28

0b00 (IDLE)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

INVALID

averaging

> CCA_LVL

B0 0x37

(0-7)

<CCA_LVL

B0 0x37

Interrupt not generated

0b01 (BUSY)

When 8 times ED value acquisition,

ED_DONE=0b1 (8 time averaging setting)

After CCA_STOP is issued,

CCA_CPU_EN, CCA_EN and,

CCA_STOP are automatically

cleared.

ED50

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA Completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_CPU_EN/CCA_EN

[CCA_CTRL: B0 0x39(5-4)]

CCA_STOP

[CCA_CTRL]B0 0x39

ED_DONE

[ED_CTRL: B0 0x41(4)]

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(1-8)

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