ML7344J datasheet(86/151 Pages) ETC2

86 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

86/151

Interrupt notice

Reference point

Timing From reference point to interrupt generation

or interrupt generation timing

INT[8]

RX completion

SyncWord detection

NRZ coding, Full trigger level is set to 0x05

27byte (Length to CRC) * 8bit * 10μs(bit cycle) = 2160μs

INT[9]

CRC error

detection

SyncWord detection

(Format A/B) each RX CRC block calculation completion

(Format C) RX completion

INT[10]

Reserved

INT[11]

RX Length error

detection

SyncWord detection

80μs (L-field 1byte)

160μs (L-field 2byte)

INT[12]

RX FIFO access

error detection

(1)overflow occurs because FIFO read is too slow.

(2)underflow occurs because too many FIFO data is read

INT[13]

SyncWord

detection

SyncWord detection

INT[14]

Field check

completion

Match or mismatch detected in Field check

INT[15]

Sync error

detection

During RX after SyncWord detection, out-of-sync detected.

(When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b00 or

0b11.)

INT[16]

TX completion

TX_ON command

(*1)

RF wake-up+[TX data+3](bit) after

=1406μs+(39byte ×10 +3 )bit * 10μs (bit cycle)=4556μs

INT[17]

TX Data request

accept completion

After full length data are written to the TX FIFO.

INT[18]

CCA completion

CCA execution start

(1)Normal mode

(ED value calculation averaging time + IDLE_WAIT setting

[IDLE_WAIT_H/L:B0 0x3B,3C] ) * AD conversion time

(2) IDLE detection mode

○IDLE judgment case

(ED value calculation averaging time + IDLE_WAIT setting

[IDLE_WAIT_H/L:B0 0x3B,3C] ) * AD conversion time

○BUSY judgment case

(ED value calculation averaging time) * AD conversion time

AD conversion time can be changed by ADC_CLK_SEL

([ADC_CLK_SET:B1 0x08(4)] ).

ADC conversion time = 14.8μs at 2.17MHz

18.5μs at 1.73MHz

For details, please refer to the “CCA (Clear Channel

Assessment) function”.

INT[19]

TX Length error

detection

After set length value to [TX_PKT_LEN_H/L: B0 0x7A/7B]

INT[20]

TX FIFO access

error detection

(1) When the next packet data is written to the TX_FIFO before

transmitting previous packet data.

(2) FIFO overflow when writing

(3) FIFO underflow (no data) when transmitting

INT[21]

Reserved

(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.

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