ML7344J datasheet(76/151 Pages) ETC2

76 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

76/151

The following is timing chart for IDLE detection mode.

Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)

Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)

Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0000 (IDLE detection 0µs)

[Upon BUSY detection, continue CCA and IDLE detection case]

NOTE:

*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL

([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.

(20-27)

(22-29)

ED value

(Internal signal)

AD conversion

(18.5μs)

ED value average period

(148μs)

0b10 (CCA on-going)

ED0

ED7

ED8

ED27

0b00 (IDLE)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

INVALID

averaging

> CCA_LVL

B0 0x37

(0-7)

<CCA_LVL

B0 0x37

Interrupt not generated

0b01 (BUSY)

After IDLE detection, CCA will be completed,

then CCA_EN, CCA_IDLE_EN are reset to

0b0 automatically.

ED29

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA Completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_IDLE_EN/CCA_EN

[CCA_CTRL: B0 0x39(6/4)]

●●●

(1-8)

●●●

ED28

(21-28)

IDLE detection period

CCA execution period (Min. 296μs + IDLE detection period)

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