ML7344J datasheet(68/151 Pages) ETC2

68 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

68/151

●Modulation setting

ML7344 supports GFSK modulation and FSK modulation.

(1) GFSK modulation setting

By setting GFSK_EN([DATA_SET1: B0 0x07(4)])=0b1, GFSK mode can be selected. In GFSK modulation,

frequency deviation can be set by [GFSK_DEV_H: B1 0x30] and [GFSK_DEV_L: B1 0x31] registers and

Gaussian filter can be set by [FSK_DEV0_H/GFIL0: B1 0x32] to [FSK_DEV3_H/GFIL6: B1 0x38] registers.

When enabling PLL 1/2 division mode by setting PLL_MODE ([PLL_DIV_SET:B1 0x1A(4)])=0b1,

calcurated with fref =FMCK1/2 in the following formula.

i) GFSK frequency deviation setting

F_DEV value can be calculated as the following formula:

⋅

⎪⎭

⎪

⎬

⎫

⎪⎩

⎪

⎨

⎧

ref

dev

DEV

(Integer part)

Here

DEV

F _

: Frequency deviation setting

dev

Frequency deviation [MHz]

ref

PLL reference frequency (= master clock frequency: FMCK1)

[Example]

When set frequency deviation to 50kH (master clock 26MHz), the calculation is as follows.

F_DEV = {0.05MHz ÷ 26MHz} ×220 (Integer value) = 2016 (0x07E0)

[GFSK_DEV_H: B1 0x30] = 0x07

[GFSK_DEV_L: B1 0x31] = 0xE0

ii) Gaussian filter setting

BT value of Gaussian filter and setting value to related registers are shown in the below table.

BT value

0.5

1.0

[FSK_DEV0_H/GFIL0: B1 0x32]

0x49

0x00

[FSK_DEV0_L/GFIL1: B1 0x33]

0xA7

0x10

[FSK_DEV1_H/GFIL2: B1 0x34]

0x0F

0x04

[FSK_DEV1_L/GFIL3: B1 0x35]

0x14

0x0D

[FSK_DEV2_H/GFIL4: B1 0x36]

0x19

0x1E

[FSK_DEV2_L/GFIL5: B1 0x37]

0x1D

0x32

[FSK_DEV3_H/GFIL6: B1 0x38]

0x1E

0x3C

NOTE:

GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK

mode, filter coefficient applies to this register. In FSK mode, frequency deviation applies to this register.

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