ML7344J datasheet(64/151 Pages) ETC2

64 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

64/151

NOTE:

The channel frequency to be selected must meet the following conditions. If the following conditions cannot

be met, please change channel #0 frequency or use other channels. If this formula cannot be met, expected

frequency is not functional or PLL may not be locked.

(FMCK1*n + 1MHz ) / N_div ≤ channel frequency ≤ (FMCK1*(n+1) – 1MHz ) / N_div

FMCK1: Master clock frequency

N_div = 1 (PLL_MODE ([PLL_DIV_SET: B1 0x1A (4)])=0b0)

2 (PLL_MODE ([PLL_DIV_SET: B1 0x1A (4)])=0b1)

n = integer

[Calculation example above “A” range]

Condition: Master clock 26MHz, N_div=1(PLL_MODE=0b0), n=16

(26*16+1)MHz ≤ channel frequency to be used ≤ (26*(16+1)-1)

→ 417 MHz ≤ channel frequency to be used ≤ 441MHz

NOTE:

“CH#0 frequency (Hz)” and “channle space (Hz)” may have error (Hz). Then the “channel frequency error

(Hz)” is defined as following formula.

Channel frequency error (Hz) =

CH#0 frequency error (Hz) + channel space error (Hz)* channel setting

When changing “channel frequency” by setting “channel setting” without “CH#0 frequency” change, the

“channel frequency error” will become larger than by setting both “CH#0 frequency” and “channel setting”. If

the “channle frequency error” is larger than expection, please consider to change “CH#0 frequency”.

Unusable Frequency

Usable Frequency

(FMCK1*n )/N_div

Frequency

(FMCK1*(n+1))/N_div

ML7344J Datasheet(PDF) 64 Page - List of Unclassifed Manufacturers