ML7344J datasheet(79/151 Pages) ETC2

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FEDL7344C/E/J-04

ML7344C/E/J

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(5) IDLE detection for longer period

When CCA IDLE detection is performed for longer time period, IDLE_WAIT[9:0]([IDLE_WAIT_L/H:B0

0x3C/3B(1-0)] can be used. By setting IDLE_WAIT [9:0], averaging period longer than the period (for

example, AD conversion16μs, 8 times average setting 128μs) can be possible.

This function can be used for IDLE determination – by counting times when average ED value becomes

smaller than CCA threshold defined by [CCA_LVL: B0 0x37] register. When counting exceed IDLE_WAIT

[9:0], IDLE is determined. If average ED value exceeds CCA threshold level, imemediately “Busy” is

determined without wait for IDLE_WAIT [9:0] period.

The following timing chart is IDLE detection setting IDLE_WAIT[9:0].

Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)

Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)

Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0011 (IDLE detection 55.5µs)

[ED value 8 timesv average IDLE detection case]

NOTE:

*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL

([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.

ED value

(internal signal)

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

AD conversion

(18.5μs)

ED value average period

(148μs)

0b10 (CCA on-going)

ED1

(0-7)

0b00 (IDLE)

averaging

CCA execution period (Min.296μs+55.5μs=351.5μs)

< CCA_LVL

B0 0x37

ED0

ED2

ED8

ED7

ED10

ED9

●●●

ED11

(1-8)

(2-9)

(3-10)

IDLE_WAIT[9:0]

[IDLE_WAIT_L\H: B0 0x3C/3B]

IDLE detection period

(55.5μs)

INVALID

0x000

0x001 0x002 0x003

IDLE_WAIT start

(average ED value < CCA_LVL)

continue for AD conversion period

3 times ( 55.5μs), then IDLE is

determined.

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