ML7344J datasheet(106/151 Pages) ETC2

106 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

106/151

●Turn on Sequence

(1) Initialization flow

In initialization status, interrupt process, registers setting, VCO calibration are necessary.

(1) Interrupt process

Upon reset, all interrupt notification settings ([INT_EN_GRP1-3: B0 0x10-0x12]) are disabled.

After hard reset is released, INT[0] (group 1: Clock stabilization completion interrupt) will be detected.

INT[0] should be enabled by [INT_EN_GRP1:B0 0x10] register.

(2) Registers setting

After hard reset is released, all registers in BANK0 and BANK1 except FIFO access registers

([WR_TX_FIFO: B0 0x7C] and [RD_FIFO: B0 0x7F]), are accessible before INT[0] notification.

(3) VCO calibration

VCO calibration is executed after setting upper and low limit of the operation frequency.

For details, please refer to the “VCO adjustment”.

START

Clock stabilized completion int. ?

INT[0] [INT_SOURCE_GRP1: B0 0x0D]

Yes

END

INT[0] clear

[INT_SOURCE_GRP1 B0 0x0D]

(2)Register setting

(1)Interrupt process

VCO calibration execution

INT_EN setting

[INT_EN_GRP1-3: B0 0x10-0x12]

(3)VCO calibration

*For details, please refer to

the ”VCO adjustment”

ML7344J Datasheet(PDF) 106 Page - List of Unclassifed Manufacturers