HM17CM256 datasheet(99/111 Pages) HYNIX

99 / 111 page

HM17CM256

- 99 -

•

SYSTEM BUS READ / WRITE TIMING (68 series CPU interface)

(write timing

(VDD=2.7

∼3.3V, Ta=-30∼+85°C)

ITEM

SYMBOL

CONDITION

MIN.

MAX.

UNIT

PORT

Address hold timing

Address setup timing

tAH6

tAS6

TBD

System cycle timing

Enable ”L” pulse width

Enable ”H” pulse width

tCYC6

tELW6

tEHW6

TBD

Data setup timing

Data hold timing

tDS6

tDH6

TBD

∼ D

(VDD=2.4

∼2.7V, Ta=-30∼+85°C)

ITEM

SYMBOL

CONDITION

MIN.

MAX.

UNIT

PORT

Address hold timing

Address setup timing

tAH6

tAS6

TBD

System cycle timing

Enable ”L” pulse width

Enable ”H” pulse width

tCYC6

tELW6

tEHW8

TBD

Data setup timing

Data hold timing

tDS6

tDH6

TBD

∼ D

(VDD=1.7

∼2.4V, Ta=-30∼+85°C)

ITEM

SYMBOL

CONDITION

MIN.

MAX.

UNIT

PORT

Address hold timing

Address setup timing

tAH6

tAS6

TBD

System cycle timing

Enable ”L” pulse width

Enable ”H” pulse width

tCYC6

tELW6

tEHW6

TBD

Data setup timing

Data hold timing

tDS6

tDH6

TBD

∼ D

notice)

All timing reference is 20% and 80% of VDD and 80%.

tAS6

tAH6

R/W

(WR)

∼ D

tEHW6

tELW6

tDS6

tDH6

tCYC6

(RD)

HM17CM256 Datasheet(PDF) 99 Page - Hynix Semiconductor

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