82802AC datasheet(15/53 Pages) INTEL

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Intel

® 82802AB/AC Firmware Hub

Datasheet

Interface

Symbol

Type

Intel

FWH

A/A Mux

Name and Function

ID[3:0]

Identification Inputs. These four pins are part of the mechanism

that allows multiple parts to be attached to the same bus. The

strapping of these pins is used to identify the component. The boot

device must have ID[3:0] = 0000, and it is recommended that all

subsequent devices use sequential up-count strapping (0001,

0010,0011,...

). These pins are pulled down with internal resistors, with

values between 20 and 100 k

Ω, when in the Intel FWH mode. Any

ID pins pulled high will exhibit a leakage current of approximately

200

µA. Any pins intended to be low may be left to float. In a single

Intel FWH system, all may be left floating.

A/A Mux = A[3:0]

FGPI[4:0]

Intel FWH General Purpose Inputs. These individual inputs can be

used for additional board flexibility. The state of these pins can be

read immediately at boot, through Intel FWH registers. These inputs

should be at their desired state before the start of the PCI clock

cycle during which the read is attempted, and they should remain at

the same level until the end of the read cycle. They may only be

used for 3.3-V signals. Unused FGPI pins must not be floated.

A/A Mux = A[10:6]

TBL#

Top Block Lock. When low, it prevents programming or block erase

to the highest addressable block (7 in a 4-Mbit, 15 in an 8-Mbit

component), regardless of the state of the lock register. TBL#-high

disables hardware write protection for the top block, though register-

based protection still applies. The status of TBL# does not affect the

status of block-locking registers.

A/A Mux = A4

WP#

Write Protect. When low, prevents programming or block erase to

all but the highest addressable block (0-6 in a 4-Mbit, 0-14 in an 8-

Mbit component), regardless of the state of the corresponding lock

registers. WP#-high disables hardware write protection for these

blocks, though register-based protection still applies. The status of

TBL# does not affect the status of block-locking registers.

A/A Mux = A5

A[0:10]

Low-Order Address Inputs. Inputs for low-order addresses during

read and write operations. Addresses are internally latched during a

write cycle. For the A/A Mux interface, these addresses are latched

by R/C# and share the same pins as the high-order address inputs.

DQ[0:7]

I/O

Data Input/Outputs. These pins receive data and commands during

CUI write cycles and transmit data during memory array, status

impedance when outputs are disabled. Data is internally latched

during a write cycle.

OE#

Output Enable. Gates the device’s outputs during a read cycle

R/C#

Row-Column Address Select. For the A/A Mux interface, this pin

determines whether the address pins are pointing to the row

addresses (A[0:10]) or the column addresses (A[11:19]).

WE#

Write Enable. Controls writes to the CUI and array blocks.

Addresses and data are latched on the rising edge of the WE#

pulse.

82802AC Datasheet(PDF) 15 Page - Intel Corporation

82802AC Datasheet(HTML) 15 Page - Intel Corporation

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