82802AC datasheet(41/53 Pages) INTEL

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Intel

® 82802AB/AC Firmware Hub

Datasheet

Table 16.

FWH Read Cycle

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]

Direction

Comments

START

1101

FWH4 must be active (low) for the part to respond.

Only the last start field (before FWH4 transitioning high)

should be recognized. The START field contents

indicate an FWH memory read cycle.

IDSEL

0000

1111

Indicates which FWH device should respond. If the

IDSEL (ID select) field matches the value ID[3:0], then

that particular device will respond to subsequent

commands.

3-9

IMADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

On multibyte data transfers, lower-order addresses will

be zero, depending on page size.

IMSIZE

0000 (1 byte)

A field of this size indicates how many bytes will be

transferred during multibyte operations. The FWH will

only support single-byte transfers.

TAR0

1111

then float

In this clock cycle, the master (Intel ICH) has driven the

bus to all 1s and then floats the bus, prior to the next

clock cycle. This is the first part of the bus “turnaround

cycle.”

TAR1

1111 (float)

Float then

OUT

The FWH takes control of the bus during this cycle.

During the next clock cycle, it will be driving “sync

data.”

13-14

WSYNC

0101 (WAIT)

OUT

The FWH outputs the value 0101, a wait-sync

(WSYNC, a.k.a. “short-sync”), for two clock cycles. This

value indicates to the master (Intel ICH) that data is not

yet available from the part. This number of wait-syncs

is a function of the device’s access time.

RSYNC

0000 (READY)

OUT

During this clock cycle, the FWH will generate a “ready-

sync” (RSYNC) indicating that the least-significant

nibble of the least-significant byte will be available

during the next clock cycle.

DATA

YYYY

OUT

YYYY is the least-significant nibble of the least-

significant data byte.

DATA

YYYY

OUT

YYYY is the most-significant nibble of the least-

significant data byte.

17+

3 x 2n-1 +

“DATA”

2 WSYNCS +

1 RSYNC +

2 DATA

OUT

n = IMSIZE. Each subsequent byte of data requires 2

wait-syncs + 1 ready-sync + 2 data nibbles.

The FWH supports only n=0000 (single-byte) reads.

+ 1

TAR0

1111

OUT

then float

In this clock cycle, the Inel FWH has driven the bus to

all ones and then floats the bus prior to the next clock

cycle. This is the first part of the bus “turnaround cycle.”

+ 1

TAR1

1111 (float)

Float then

The master (Intel ICH) resumes control of the bus

during this cycle.

Note:

1. Field contents are valid on the rising edge of the present clock cycle.

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