82802AC datasheet(23/53 Pages) INTEL

23 / 53 page

Intel

® 82802AB/AC Firmware Hub

Datasheet

4.7.

Block Erase Suspend Command

The Block Erase Suspend command allows block-erase interruption to read or program data in another

block of memory. Once the block erase process starts, writing the Block Erase Suspend command

requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The

device outputs status register data when read after the Block Erase Suspend command is written. Polling

the status register can help determine when the block erase operation was suspended.

After a successful suspend, a Read Array command may be written to read data from a block other than

the suspended block. A Program command sequence may also be issued during erase suspend to program

data in blocks other that the block currently in the erase suspend mode.

The other valid commands while block erase is suspended include Read Status Register and Block Erase

Resume. After a Block Erase Resume command is written, the WSM will continue the block erase

process. VPP must remain at VPPH1/2 (the same VPP level initially used for the block erase) while block

erase is suspended. RST# or INIT# must also remain at VIH. Block erase cannot resume until program

operations initiated during block erase suspend have completed.

4.8.

Program Suspend Comand

The Program Suspend command allows program interruption to read data in other memory locations.

Once the program process starts, writing the Program Suspend command requests that the WSM suspend

the program sequence at a predetermined point in the algorithm. The device continues to output status

help determine when the program operation was suspended.

After a successful suspend, a Read Array command can be written to read data from locations other than

that which is suspended. The only other valid commands while program is suspended are Read Status

programming process. V

PP must remain at VPPH1/2 (the same VPP level used for program) while in program

suspend mode. RST# or INIT# must also remain at VIH.

4.9.

Random Number Generator Registers

A series of registers are available in the Intel FWH to provide software read- and write-locking and GPI

feedback. Also available are the set of control registers for controlling and gathering random numbers.

These registers are accessible through standard addressable memory space (see the following table).

It is recommended that the GPI pins be in the desired state before FWH4 is brought low for the

beginning of the next bus cycle, and remain in that state until the end of the read.

82802AC Datasheet(PDF) 23 Page - Intel Corporation