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82802AC Datasheet(PDF) 5 Page - Intel Corporation |
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82802AC Datasheet(HTML) 5 Page - Intel Corporation |
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5 / 53 page ![]() Intel ® 82802AB/AC Firmware Hub R Datasheet 5 Figures Figure 1. Simplified Block Diagram ..................................................................................... 8 Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture .................... 11 Figure 3. Intel FWH Boot-Configuration System Memory Map......................................... 11 Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout......................................................... 13 Figure 5. 40-Lead TSOP Intel Firmware Hub Pinout ........................................................ 13 Figure 6. Automated Block Erase Flowchart..................................................................... 31 Figure 7. Clock Waveform ................................................................................................ 37 Figure 8. Output Timing Parameters................................................................................. 38 Figure 9. Input Timing Parameters ................................................................................... 39 Figure 10. FWH Single-Byte Read Waveforms .................................................................. 42 Figure 11. Write Waveforms ............................................................................................... 43 Figure 12. Intel FWH Output Timing Parameters ............................................................... 45 Figure 13. Intel FWH Input Timing Parameters .................................................................. 46 Figure 14. A/A Mux Read Timing Diagram ......................................................................... 50 Figure 15. A/A Mux Write Timing Diagram ......................................................................... 52 Tables Table 1. Pin Descriptions ................................................................................................. 14 Table 2. Command Definitions......................................................................................... 19 Table 3. Status Register Definition .................................................................................. 20 Table 4. Identifier Codes.................................................................................................. 21 Table 5. Intel Firmware Hub Register Configuration Map................................................ 24 Table 6. Register-Based Locking Value Definitions......................................................... 25 Table 7. Temperature and VCC....................................................................................... 33 Table 8. Intel FWH Interface DC Input/Output Specifications.......................................... 34 Table 9. Power Supply Specifications — All Interfaces ................................................... 35 Table 10. Intel FWH Interface AC Input/Output Specifications.......................................... 36 Table 11. Clock Specification............................................................................................. 37 Table 12. Signal Timing Parameters.................................................................................. 38 Table 13. Interface Measurement Condition Parameters .................................................. 39 Table 14. AC Waveform for Reset Operation.................................................................... 39 Table 15. Programming Times .......................................................................................... 40 Table 16. FWH Read Cycle ............................................................................................... 41 Table 17. FWH Write Cycle ............................................................................................... 42 Table 18. Signal Timing Parameters.................................................................................. 44 Table 19. RNG Timing Characteristics .............................................................................. 45 Table 20. RNG Statistical Characteristics.......................................................................... 45 Table 21. Bus Operations .................................................................................................. 48 |
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