82802AC datasheet(42/53 Pages) INTEL

42 / 53 page

Intel

® 82802AB/AC Firmware Hub

Datasheet

5.4.1.2.

Single-Byte Read Waveforms

Figure 10.

FWH Single-Byte Read Waveforms

IMADDR

STR

CLK

FWH[3:0]

FWH4

IDS

IMS

TAR

SYNC(3)

DATA

TAR

5.4.1.3.

Write Cycle Sequence

The firmware hub only supports single-byte writes. Each byte represents either the data to be written or a

valid flash command. Refer to the waveforms in Figure 11.

Table 17.

FWH Write Cycle

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]

Direction

Comments

START

1110

FWH4 must be active (low) for the part to respond.

Only the last start field (before FWH4 transitioning

high) should be recognized. The START field

contents indicate an FWH memory write cycle.

IDSEL

0000

1111

Indicates which FWH device should respond. If the

IDSEL (ID select) field matches the value ID[3:0],

then that particular device will respond to subsequent

commands.

3-9

IMADDR

YYYY

These seven clock cycles make up the 28-bit

memory address. YYYY is one nibble of the entire

address. Addresses are transferred most-significant

nibble first.

IMSIZE

0000 (1 byte)

This size field indicates how many bytes will be

transferred during read/write operations. The FWH

only supports single-byte writes.

DATA

YYYY

This field is the least-significant nibble of the data

byte. This data is either the data to be programmed

into the flash memory or any valid flash command.

DATA

YYYY

This field is the most-significant nibble of the data

byte.

TAR0

1111

then float

In this clock cycle, the master (Intel ICH) has driven

the bus to all 1s and then floats the bus prior to the

next clock cycle. This is the first part of the bus

“turnaround cycle.”

TAR1

1111 (float)

Float then

OUT

The FWH takes control of the bus during this cycle.

During the next clock cycle it will be driving the “sync”

data.

RSYNC

0000

OUT

The FWH outputs the values 0000, indicating that it

has received data or a flash command.

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