M80C286 datasheet(18/60 Pages) INTEL

18 / 60 page

M80C286

PRIVILEGE LEVEL CHANGES

Any control transfer that changes CPL within the

task causes a change of stacks as part of the oper-

ation Initial values of SSSP for privilege levels 0 1

and 2 are kept in the task state segment (refer to

Task Switch Operation) During a JMP or CALL con-

trol transfer the new stack pointer is loaded into the

SS and SP registers and the previous stack pointer

is pushed onto the new stack

When returning to the original privilege level its

stack is restored as part of the RET or IRET instruc-

tion operation For subroutine calls that pass param-

eters on the stack and cross privilege levels a fixed

number of words as specified in the gate are cop-

ied from the previous stack to the current stack The

inter-segment RET instruction with a stack adjust-

ment value will correctly restore the previous stack

pointer upon return

Protection

The M80C286 includes mechanisms to protect crit-

ical instructions that affect the CPU execution state

(eg HLT) and code or data segments from improper

usage These protection mechanisms are grouped

into three forms

Restricted

usage of segments (eg no write al-

lowed to read-only data segments) The only seg-

ments available for use are defined by descrip-

tors in the Local Descriptor Table (LDT) and

Global Descriptor Table (GDT)

Restricted

access to segments via the rules of

privilege and descriptor usage

Privileged instructions or operations that may

only be executed at certain privilege levels as de-

termined by the CPL and IO Privilege Level

(IOPL) The IOPL is defined by bits 14 and 13 of

the flag word

These checks are performed for all instructions and

can be split into three categories segment load

checks (Table 11) operand reference checks (Table

12) and privileged instruction checks (Table 13)

Any violation of the rules shown will result in an ex-

ception A not-present exception related to the stack

segment causes exception 12

The IRET and POPF instructions do not perform

some of their defined functions if CPL is not of suffi-

cient privilege (numerically small enough) Precisely

these are

The IF bit is not changed if CPL l IOPL

The IOPL field of the flag word is not changed if

CPL l 0

No exceptions or other indication are given when

these conditions occur

Table 11 Segment Register Load Checks

Error Description

Exception

Number

Descriptor table limit exceeded

Segment descriptor not-present

11 or 12

Privilege rules violated

Invalid descriptorsegment type seg-

ment register load

Read only data segment load to

Special Control descriptor load to

DS ES SS

Execute only segment load to

DS ES SS

Data segment load to CS

ReadExecute code segment

load to SS

Table 12 Operand Reference Checks

Error Description

Exception

Number

Write into code segment

Read from execute-only code

segment

Write to read-only data segment

Segment limit exceeded1

12 or 13

NOTE

Carry out in offset calculations is ignored

Table 13 Privileged Instruction Checks

Error Description

Exception

Number

CPL i 0 when executing the following

instructions

LIDT LLDT LGDT LTR LMSW

CTS HLT

CPL l IOPL when executing the fol-

lowing instructions

INS IN OUTS OUT STI CLI

LOCK

EXCEPTIONS

The M80C286 detects several types of exceptions

and interrupts in protected mode (see Table 14)

Most are restartable after the exceptional condition

is removed Interrupt handlers for most exceptions

can read an error code pushed on the stack after

the return address that identifies the selector in-

volved (0 if none) The return address normally

points to the failing instruction including all leading

prefixes For a processor extension segment over-

run exception the return address will not point at the

ESC instruction that caused the exception however

the processor extension registers may contain the

address of the failing instruction

M80C286 Datasheet(PDF) 18 Page - Intel Corporation

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